The Experts below are selected from a list of 18354 Experts worldwide ranked by ideXlab platform
Berkehan Ciftcioglu - One of the best experts on this subject based on the ideXlab platform.
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3 d integrated heterogeneous intra chip free space Optical Interconnect
Optics Express, 2012Co-Authors: Berkehan Ciftcioglu, Rebecca Berman, Ioannis Savidis, Shang Wang, Eby G. Friedman, Manish Jain, Michael C Huang, Duncan T Moore, G W WicksAbstract:This paper presents the first chip-scale demonstration of an intra-chip free-space Optical Interconnect (FSOI) we recently proposed. This Interconnect system provides point-to-point free-space Optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based Optical Interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI Interconnect, and compare it to a waveguide-based Optical Interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured Optical transmission loss is 5 dB, the crosstalk is less than −20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.
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A 3-D integrated intrachip free-space Optical Interconnect for many-core chips
IEEE Photonics Technology Letters, 2011Co-Authors: Berkehan Ciftcioglu, Rebecca Berman, Zach Darling, Gary Wicks, Duncan Moore, Alok Garg, Jianyun Hu, Ioannis Savidis, Shang Wang, Michael Huang, Eby G. Friedman, Manish Jain, Jing Xue, Jian Zhang, Hui WuAbstract:This letter presents a new Optical Interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an Optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and ${-}$26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.
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an intra chip free space Optical Interconnect
International Symposium on Computer Architecture, 2010Co-Authors: Jing Xue, Rebecca Berman, Alok Garg, Berkehan Ciftcioglu, Ioannis Savidis, Shang Wang, Manish Jain, Peng Liu, Michael C Huang, Eby G. FriedmanAbstract:Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal Interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip Interconnect technologies. Optical Interconnect is a promising long term solution. However, while significant progress in Optical signaling has been made in recent years, networking issues for on-chip Optical Interconnect still require much investigation. Taking the underlying Optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of Optical Interconnects. In this paper, we propose and study the design of a fully distributed Interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The Interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.
Chiachi Chang - One of the best experts on this subject based on the ideXlab platform.
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Implementation of Chip-Level Optical Interconnect With Laser and Photodetector Using SOI-Based 3-D Guided-Wave Path
IEEE Photonics Journal, 2014Co-Authors: Pokuan Shen, Chinta Chen, Chiachi Chang, Chia-hao Chang, Chien-yu Chiu, Sheng-long Li, Mount-learn WuAbstract:A chip-level Optical Interconnect module combined with a vertical-cavity surface-emitting laser (VCSEL) chip, a photodetector (PD) chip, a driver integrated circuit (IC), and an amplifier IC on a silicon-on-insulator (SOI) substrate with 3-D guided-wave paths is experimentally demonstrated. Such an Optical Interconnect is developed for the signal connection in multicore processors or memory-to-processor interfaces. The 3-D guided-wave path, consisting of silicon-based 45° microreflectors and trapezoidal waveguides, is used to connect the Optical signal between transmitter and receiver. In this paper, the VCSEL and PIN PD chips are flip-chip integrated on a SOI substrate to achieve complete chip-level Optical Interconnects. Due to the unique 3-D guided-wave path design, a higher laser-to-PD Optical coupling efficiency of -2.19 dB and a larger alignment tolerance of ±10μm for the VCSEL/PD assembly are achieved. The measured laser-to-PD Optical transmission efficiency can reach -2.19 dB, and the maximum Optical power and threshold current of VCSEL is 3.27 mW and 1 mA, respectively. To verify the data transmission, the commercial driver IC and amplifier IC are assembled upon the silicon chip, and the error-free data transmission of 10 Gbps can be achieved when the VCSEL is operated at the driving current of 9 mA.
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Optical Interconnect transmitter based on guided wave silicon Optical bench
Optics Express, 2012Co-Authors: Pokuan Shen, Chinta Chen, Chiachi Chang, Hsuliang Hsiao, Yenchung Chang, Hoyen Tsai, Hsiaochin Lan, Yunchih LeeAbstract:An Optical Interconnect transmitter based on guided-wave silicon Optical bench is demonstrated. The guided-wave silicon Optical bench (GW-SiOB) is developed on a silicon-on-insulator (SOI) substrate. The three-dimensional guided-wave Optical paths on the silicon Optical bench are realized using trapezoidal waveguides monolithically integrated with 45° micro-reflectors. Such three-dimensional guided-w ave Optical paths of SiOB would simplify and shrink the intra-chip Optical Interconnects located on a SOI substrate. The clearly open eye patterns operated at a data rate of 5 Gbps verifies the proposed GW-SiOB is suitable for intra-chip Optical Interconnects.
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compact and passive alignment 4 channel 2 5 gbps Optical Interconnect modules based on silicon Optical benches with 45 micro reflectors
Optics Express, 2009Co-Authors: Hsuliang Hsiao, Chiachi Chang, Hsiaochin Lan, Chiayu Lee, Siouping Chen, Chihhung Hsu, Shuofu Chang, Yoshen Lin, Fengming Kuo, Jinwei ShiAbstract:Compact and passive-alignment 4-channel × 2.5-Gbps Optical Interconnect modules are developed based on the silicon Optical benches (SiOBs) of 5 × 5 mm2. A silicon-based 45° micro-reflector and V-groove arrays are fabricated on the SiOB using anisotropic wet etching. Moreover, high-frequency transmission lines of 4 channel × 2.5 Gbps, and bonding pads with Au/Sn eutectic solder are also deposited on the SiOB. The vertical-cavity surface-emitting laser (VCSEL) array and photo-detector (PD) array are flip-chip assembled on the intended positions. The multi-mode fiber (MMF) ribbons are passively aligned and mounted onto the V-groove arrays. Without the assistance of additional optics, the coupling efficiencies of VCSEL-to-MMF in the transmitting part and MMF-to-PD in the receiving part can be as high as −5.65 and −1.98 dB, respectively, under an Optical path of 180 μm. The 1-dB coupling tolerance of greater than ± 20 μm is achieved for both transmitting and receiving parts. Eye patterns of both parts are demonstrated using 15-bit PRBS at 2.5 Gbps.
Eby G. Friedman - One of the best experts on this subject based on the ideXlab platform.
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3 d integrated heterogeneous intra chip free space Optical Interconnect
Optics Express, 2012Co-Authors: Berkehan Ciftcioglu, Rebecca Berman, Ioannis Savidis, Shang Wang, Eby G. Friedman, Manish Jain, Michael C Huang, Duncan T Moore, G W WicksAbstract:This paper presents the first chip-scale demonstration of an intra-chip free-space Optical Interconnect (FSOI) we recently proposed. This Interconnect system provides point-to-point free-space Optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based Optical Interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI Interconnect, and compare it to a waveguide-based Optical Interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured Optical transmission loss is 5 dB, the crosstalk is less than −20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.
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A 3-D integrated intrachip free-space Optical Interconnect for many-core chips
IEEE Photonics Technology Letters, 2011Co-Authors: Berkehan Ciftcioglu, Rebecca Berman, Zach Darling, Gary Wicks, Duncan Moore, Alok Garg, Jianyun Hu, Ioannis Savidis, Shang Wang, Michael Huang, Eby G. Friedman, Manish Jain, Jing Xue, Jian Zhang, Hui WuAbstract:This letter presents a new Optical Interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an Optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and ${-}$26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.
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an intra chip free space Optical Interconnect
International Symposium on Computer Architecture, 2010Co-Authors: Jing Xue, Rebecca Berman, Alok Garg, Berkehan Ciftcioglu, Ioannis Savidis, Shang Wang, Manish Jain, Peng Liu, Michael C Huang, Eby G. FriedmanAbstract:Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal Interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip Interconnect technologies. Optical Interconnect is a promising long term solution. However, while significant progress in Optical signaling has been made in recent years, networking issues for on-chip Optical Interconnect still require much investigation. Taking the underlying Optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of Optical Interconnects. In this paper, we propose and study the design of a fully distributed Interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The Interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.
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on chip Optical Interconnect for reduced delay uncertainty
Nano-Net '07 Proceedings of the 2nd international conference on Nano-Networks, 2007Co-Authors: Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas A Nelson, P M Fauchet, David H Albonesi, Eby G. FriedmanAbstract:Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip Interconnects have become increasingly stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper Interconnect to satisfy a variety of design requirements. On-chip Optical Interconnect has been considered as a potential partial substitute for electrical Interconnect. In this paper, predictions of the performance of CMOS compatible Optical devices are made based on current state-of-the-art Optical technologies. Based on these predictions, the delay uncertainty in electrical and Optical Interconnects is analyzed, and shown to affect both the latency and bandwidth of the Interconnect. The two Interconnects are also compared for latency, power, and bandwidth density.
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predictions of cmos compatible on chip Optical Interconnect
System-Level Interconnect Prediction, 2005Co-Authors: Guoqing Chen, Eby G. Friedman, Hui Chen, Mikhail Haurylau, Nicholas A Nelson, P M Fauchet, David H AlbonesiAbstract:Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper Interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip Optical Interconnect has been considered as a potential substitute for electrical Interconnect in the past two decades. In this paper, predictions of the performance of CMOS compatible Optical devices are made based on current state-of-art Optical technologies. Electrical and Optical Interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which Optical Interconnect becomes advantageous over electrical Interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node.
Pokuan Shen - One of the best experts on this subject based on the ideXlab platform.
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Implementation of Chip-Level Optical Interconnect With Laser and Photodetector Using SOI-Based 3-D Guided-Wave Path
IEEE Photonics Journal, 2014Co-Authors: Pokuan Shen, Chinta Chen, Chiachi Chang, Chia-hao Chang, Chien-yu Chiu, Sheng-long Li, Mount-learn WuAbstract:A chip-level Optical Interconnect module combined with a vertical-cavity surface-emitting laser (VCSEL) chip, a photodetector (PD) chip, a driver integrated circuit (IC), and an amplifier IC on a silicon-on-insulator (SOI) substrate with 3-D guided-wave paths is experimentally demonstrated. Such an Optical Interconnect is developed for the signal connection in multicore processors or memory-to-processor interfaces. The 3-D guided-wave path, consisting of silicon-based 45° microreflectors and trapezoidal waveguides, is used to connect the Optical signal between transmitter and receiver. In this paper, the VCSEL and PIN PD chips are flip-chip integrated on a SOI substrate to achieve complete chip-level Optical Interconnects. Due to the unique 3-D guided-wave path design, a higher laser-to-PD Optical coupling efficiency of -2.19 dB and a larger alignment tolerance of ±10μm for the VCSEL/PD assembly are achieved. The measured laser-to-PD Optical transmission efficiency can reach -2.19 dB, and the maximum Optical power and threshold current of VCSEL is 3.27 mW and 1 mA, respectively. To verify the data transmission, the commercial driver IC and amplifier IC are assembled upon the silicon chip, and the error-free data transmission of 10 Gbps can be achieved when the VCSEL is operated at the driving current of 9 mA.
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Optical Interconnect transmitter based on guided wave silicon Optical bench
Optics Express, 2012Co-Authors: Pokuan Shen, Chinta Chen, Chiachi Chang, Hsuliang Hsiao, Yenchung Chang, Hoyen Tsai, Hsiaochin Lan, Yunchih LeeAbstract:An Optical Interconnect transmitter based on guided-wave silicon Optical bench is demonstrated. The guided-wave silicon Optical bench (GW-SiOB) is developed on a silicon-on-insulator (SOI) substrate. The three-dimensional guided-wave Optical paths on the silicon Optical bench are realized using trapezoidal waveguides monolithically integrated with 45° micro-reflectors. Such three-dimensional guided-w ave Optical paths of SiOB would simplify and shrink the intra-chip Optical Interconnects located on a SOI substrate. The clearly open eye patterns operated at a data rate of 5 Gbps verifies the proposed GW-SiOB is suitable for intra-chip Optical Interconnects.
Hugo Thienpont - One of the best experts on this subject based on the ideXlab platform.
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Optomechanical Monte Carlo Tolerancing Study of a Packaged Free-Space Intra-MCM Optical Interconnect System
IEEE Journal of Selected Topics in Quantum Electronics, 2006Co-Authors: Michael Vervaeke, Bart Volckaerts, Christof Debaes, Hugo ThienpontAbstract:We report on the performance of an intra-multichip-module free-space Optical Interconnect that integrates microlenses and a deflection prism above a dense optoelectronic chip, under various fabrication and assembly errors. This paper describes the results of a combination of mechanical Monte Carlo analysis and Optical simulations. Both the technological requirements to ensure a high process yield, and the specifications of the technology we use at our laboratories to fabricate the microOptical and micromechanical components, deep lithography with protons (DLP), are discussed. Therefore, we first conduct a sensitivity analysis that is subsequently used to set the variances of the random perturbations of the Monte Carlo simulation. By scaling these variances, we are able to investigate the effect of a technology accuracy enhancement on the fabrication and assembly yield. We estimate that 40% of the systems fabricated with DLP will show an Optical transmission efficiency above -4.32 dB, which is -3.02 dB below the theoretical obtainable value. In this paper, we also discuss our efforts to implement an optomechanical Monte Carlo simulator. It allows us to deal with specific issues not directly related with the microOptical or DLP components, such as the influence of gluing layers and structures that allow for self-alignment, by combining mechanical tolerancing algorithms with Optical simulation software. In particular, we determine that DLP provides ample accuracy to meet the requirements of a high manufacturing yield (around 91% meet an Optical transmission that is -0.75 dB below the theoretical maximum). The adhesive bonding of optoelectronic devices in their package, however, is subject to further improvement to enhance the tilt accuracy of the devices with respect to the Optical Interconnect modules
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laser ablation of parallel Optical Interconnect waveguides
IEEE Photonics Technology Letters, 2006Co-Authors: G Van Steenberge, Hugo Thienpont, Nina Hendrickx, Erwin Bosman, J Van Erps, P Van DaeleAbstract:Excimer laser ablation is presented as an alternative technology to photolithography for the fabrication of board-level parallel Optical Interconnect waveguides. Arrays of polymer multimode waveguides with a 50/spl times/50 /spl mu/m/sup 2/ cross section on a 125-/spl mu/m pitch are fully characterized. Root mean square sidewall roughness is 35 nm; no deposition of debris is observed on scanning electron microscope images. The first conclusion out of loss spectrum measurements is a "yellowing effect" of laser ablated waveguides, leading to an increased loss at shorter wavelengths. The second important conclusion is a potential low loss at a wavelength of 850, 980, and 1310 nm. This is verified at 850 nm by cutback measurements on 10-cm-long waveguides showing an average propagation loss of 0.13 dB/cm.
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Packaging a free-space intra-chip Optical Interconnect module: Monte Carlo tolerance study and assembly results
Micro-Optics VCSELs and Photonic Interconnects II: Fabrication Packaging and Integration, 2006Co-Authors: Michael Vervaeke, Mikko Karpinnen, Bart Volckaerts, Pentti Karioja, Markku Lahti, Christof Debaes, Hugo ThienpontAbstract:In this paper we give an overview of the fabrication and assembly induced performance degradation of an intra-multi-chip-module free-space Optical Interconnect, integrating micro-lenses and a deflection prism above a dense opto-electronic chip. The proposed component is used to demonstrate the capabilities of an accurate micro-Optical rapid prototype technique, namely the Deep Proton Writing (DPW). To evaluate the accuracy of DPW and to assess whether our assembly scheme will provide us with a reasonable process yield, we have built a simulation framework combining mechanical Monte Carlo analysis with Optical simulations. Both the technological requirements to ensure a high process yield, and the specifications of our in-house DPW technology are discussed. Therefore, we first conduct a sensitivity analysis and we subsequently simulate the effect of combined errors using a Monte Carlo simulation. We are able to investigate the effect of a technology accuracy enhancement on the fabrication and assembly yield by scaling the standard deviation of the errors proportionally to each sensitivity interval. We estimate that 40% of the systems fabricated with DPW will show an Optical transmission efficiency above -4.32 dB, which is -3 dB below the theoretical obtainable value. We also discuss our efforts to implement an opto-mechanical Monte Carlo simulator. It enables us to address specific issues not directly related with the micro-Optical or DPW components, such as the influence of glueing layers and structures that allow for self-alignment, by combining mechanical tolerancing algorithms with Optical simulation software. More in particular we determined that DPW provides ample accuracy to meet the requirements to obtain a high manufacturing yield. Finally, we shortly highlight the basic layout of a completed demonstrator. The adhesive bonding of opto-electronic devices in their package is subject to further improvement to enhance the tilt accuracy of the devices with respect to the Optical Interconnect modules.
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Chip-scale Optical Interconnects
Frontiers in Optics 2004 Laser Science XXII Diffractive Optics and Micro-Optics Optical Fabrication and Testing, 2004Co-Authors: Hugo Thienpont, Michael Vervaeke, Bart Volckaerts, Christof Debaes, Lieven Desmet, Heidi Ottevaere, P. Vynck, Jürgen Van Erps, Alex HermanneAbstract:We present and discuss different approaches and technologies for Optical Interconnects to Silicon chips with a focus on low-cost, chip-compatible, three-dimensional free-space plastic micro-Optical Interconnect modules.
