The Experts below are selected from a list of 3375 Experts worldwide ranked by ideXlab platform
Vladlen Koltun - One of the best experts on this subject based on the ideXlab platform.
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Semi-Parametric Image Synthesis
2018 IEEE CVF Conference on Computer Vision and Pattern Recognition, 2018Co-Authors: Xiaojuan Qi, Qifeng Chen, Vladlen KoltunAbstract:We present a semi-parametric approach to photographic image synthesis from semantic layouts. The approach combines the complementary strengths of parametric and nonparametric techniques. The nonparametric component is a Memory Bank of image segments constructed from a training set of images. Given a novel semantic layout at test time, the Memory Bank is used to retrieve photographic references that are provided as source material to a deep network. The synthesis is performed by a deep network that draws on the provided photographic material. Experiments on multiple semantic segmentation datasets show that the presented approach yields considerably more realistic images than recent purely parametric techniques.
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CVPR - Semi-Parametric Image Synthesis
2018 IEEE CVF Conference on Computer Vision and Pattern Recognition, 2018Co-Authors: Xiaojuan Qi, Qifeng Chen, Vladlen KoltunAbstract:We present a semi-parametric approach to photographic image synthesis from semantic layouts. The approach combines the complementary strengths of parametric and nonparametric techniques. The nonparametric component is a Memory Bank of image segments constructed from a training set of images. Given a novel semantic layout at test time, the Memory Bank is used to retrieve photographic references that are provided as source material to a deep network. The synthesis is performed by a deep network that draws on the provided photographic material. Experiments on multiple semantic segmentation datasets show that the presented approach yields considerably more realistic images than recent purely parametric techniques.
Mahmut Kandemir - One of the best experts on this subject based on the ideXlab platform.
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Improving Bank-level parallelism for irregular applications
2016 49th Annual IEEE ACM International Symposium on Microarchitecture (MICRO), 2016Co-Authors: Xulong Tang, Mahmut Kandemir, Praveen Yedlapalli, Jagadish KotraAbstract:Observing that large multithreaded applications with irregular data access patterns exhibit very low Memory Bank-level parallelism (BLP) during their execution, we propose a novel loop iteration scheduling strategy built upon the inspector-executor paradigm. A unique characteristic of this strategy is that it considers both Bank-level parallelism (from an inter-core perspective) and Bank reuse (from an intra-core perspective) in a unified framework. Its primary goal is to improve Bank-level parallelism, and Bank reuse is taken into account only if doing so does not hurt Bank-level parallelism. Our experiments with this strategy using eight application programs on both a simulator and a real multicore system show an average BLP improvement of 46.8% and an average execution time reduction of 18.3%.
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MICRO - Compiler Support for Optimizing Memory Bank-Level Parallelism
2014 47th Annual IEEE ACM International Symposium on Microarchitecture, 2014Co-Authors: Wei Ding, Diana Guttman, Mahmut KandemirAbstract:Many prior compiler-based optimization schemes focused exclusively on cache data locality. However, cache locality is only one part of the overall performance of applications running on emerging multicores or many cores. For example, Memory stalls could constitute a very large fraction of execution time even in cache-optimized codes, and one of the main reasons for this is lack of Memory-level parallelism. Motivated by this, we propose a compiler-based Bank-Level Parallelism (BLP) optimization scheme that uses loop tile scheduling. More specifically, we first use Cache Miss Equations to predict where the last-level cache miss will happen in each tile, and then identify the set of Memory Banks that will be accessed in each tile. Using this information, two tile scheduling algorithms are proposed to maximize BLP, each targeting a different scenario. We further discuss how our compiler-based scheme can be enhanced to consider Memory controller-level parallelism and row-buffer locality. Our experimental evaluation using 11 multithreaded applications shows that the proposed BLP optimization can improve average BLP by 17.1% on average, resulting in a 9.2% reduction in average Memory access latency. Furthermore, considering Memory controller-level parallelism and row-buffer locality (in addition to BLP) takes our average improvement in Memory access latency to 22.2%.
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Compiler Support for Optimizing Memory Bank-Level Parallelism
2014 47th Annual IEEE ACM International Symposium on Microarchitecture, 2014Co-Authors: Wei Ding, Diana Guttman, Mahmut KandemirAbstract:Many prior compiler-based optimization schemes focused exclusively on cache data locality. However, cache locality is only one part of the overall performance of applications running on emerging multicores or many cores. For example, Memory stalls could constitute a very large fraction of execution time even in cache-optimized codes, and one of the main reasons for this is lack of Memory-level parallelism. Motivated by this, we propose a compiler-based Bank-Level Parallelism (BLP) optimization scheme that uses loop tile scheduling. More specifically, we first use Cache Miss Equations to predict where the last-level cache miss will happen in each tile, and then identify the set of Memory Banks that will be accessed in each tile. Using this information, two tile scheduling algorithms are proposed to maximize BLP, each targeting a different scenario. We further discuss how our compiler-based scheme can be enhanced to consider Memory controller-level parallelism and row-buffer locality. Our experimental evaluation using 11 multithreaded applications shows that the proposed BLP optimization can improve average BLP by 17.1% on average, resulting in a 9.2% reduction in average Memory access latency. Furthermore, considering Memory controller-level parallelism and row-buffer locality (in addition to BLP) takes our average improvement in Memory access latency to 22.2%.
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Off-chip access localization for NoC-based multicores
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012Co-Authors: Wei Ding, Mahmut Kandemir, Yuanrui Zhang, Emre KultursayAbstract:In a network-on-chip based multicore, an off-chip data access needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the Memory access itself). Further, it also causes additional delays for on-chip accesses by creating contention on network resources. In this paper, we propose a compiler-guided off-chip data access localization strategy to ensure that, an off-chip access traverses a small number of links (hops) to reach the Memory controller which governs the Memory Bank that holds the requested data. The results collected clearly emphasize the importance of localizing off-chip accesses.
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DATE - Using dynamic compilation for continuing execution under reduced Memory availability
2009 Design Automation & Test in Europe Conference & Exhibition, 2009Co-Authors: Ozcan Ozturk, Mahmut KandemirAbstract:This paper explores the use of dynamic compilation for continuing execution even if one or more of the Memory Banks used by an application become temporarily unavailable (but their contents are preserved), that is, the number of Memory Banks available to the application varies at runtime. We implemented the proposed dynamic compilation approach using a code instrumentation system and performed experiments with 12 embedded benchmark codes. The results collected so far are very encouraging and indicate that, even when all the overheads incurred by dynamic compilation are included, the proposed approach still brings significant benefits over an alternate approach that suspends application execution when there is a reduction in Memory Bank availability and resumes later when all the Banks are up and running.
Hon Nin Cheung - One of the best experts on this subject based on the ideXlab platform.
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Hardware implementation of the depth first search bit stream SPIHT system
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001Co-Authors: Hon Nin CheungAbstract:In this paper, we present a hardware implementation of an embedded wavelet coding system using the Set Partitioning in Hierarchical Trees (SPIHT) algorithm. The coding system can be switched to perform encoding and decoding on the same device. The input into the system during encoding is a stream of image pixels and the output is an encoded bit stream ready for transmission. The system produces the reconstructed image data from the received bit stream during decoding. The coding system consists of discrete wavelet transform (DWT) and IDWT modules and tree searching quantization (TS) and ITS modules. It uses two Memory Banks for processing: coefficient Memory Bank and subtree Memory Bank. To reduce storage requirements, the coefficient Memory Bank is used at different stages of processing to store the image pixels or wavelet coefficients. In the encoding stage, the coefficient Memory Bank contains the image pixels initially. After the DWT is performed, the Memory Bank contains the wavelet coefficients. During decoding, the coefficient Memory Bank stores the reconstructed coefficients and after the IDWT contains the decoded image pixels.
Xiaojuan Qi - One of the best experts on this subject based on the ideXlab platform.
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Semi-Parametric Image Synthesis
2018 IEEE CVF Conference on Computer Vision and Pattern Recognition, 2018Co-Authors: Xiaojuan Qi, Qifeng Chen, Vladlen KoltunAbstract:We present a semi-parametric approach to photographic image synthesis from semantic layouts. The approach combines the complementary strengths of parametric and nonparametric techniques. The nonparametric component is a Memory Bank of image segments constructed from a training set of images. Given a novel semantic layout at test time, the Memory Bank is used to retrieve photographic references that are provided as source material to a deep network. The synthesis is performed by a deep network that draws on the provided photographic material. Experiments on multiple semantic segmentation datasets show that the presented approach yields considerably more realistic images than recent purely parametric techniques.
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CVPR - Semi-Parametric Image Synthesis
2018 IEEE CVF Conference on Computer Vision and Pattern Recognition, 2018Co-Authors: Xiaojuan Qi, Qifeng Chen, Vladlen KoltunAbstract:We present a semi-parametric approach to photographic image synthesis from semantic layouts. The approach combines the complementary strengths of parametric and nonparametric techniques. The nonparametric component is a Memory Bank of image segments constructed from a training set of images. Given a novel semantic layout at test time, the Memory Bank is used to retrieve photographic references that are provided as source material to a deep network. The synthesis is performed by a deep network that draws on the provided photographic material. Experiments on multiple semantic segmentation datasets show that the presented approach yields considerably more realistic images than recent purely parametric techniques.
Yi Yang - One of the best experts on this subject based on the ideXlab platform.
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Few-Shot Object Recognition from Machine-Labeled Web Images
2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2017Co-Authors: Zhongwen Xu, Yi YangAbstract:With the tremendous advances made by Convolutional Neural Networks (ConvNets) on object recognition, we can now easily obtain adequately reliable machine-labeled annotations easily from predictions by off-the-shelf ConvNets. In this work, we present an abstraction Memory based framework for few-shot learning, building upon machine-labeled image annotations. Our method takes large-scale machine-annotated dataset (e.g., OpenImages) as an external Memory Bank. In the external Memory Bank, the information is stored in the Memory slots in the form of key-value, in which image feature is regarded as the key and the label embedding serves as the value. When queried by the few-shot examples, our model selects visually similar data from the external Memory Bank and writes the useful information obtained from related external data into another Memory Bank, i.e., abstraction Memory. Long Short-Term Memory (LSTM) controllers and attention mechanisms are utilized to guarantee the data written to the abstraction Memory correlates with the query example. The abstraction Memory concentrates information from the external Memory Bank to make the few-shot recognition effective. In the experiments, we first confirm that our model can learn to conduct few-shot object recognition on clean human-labeled data from the ImageNet dataset. Then, we demonstrate that with our model, machine-labeled image annotations are very effective and abundant resources for performing object recognition on novel categories. Experimental results show that our proposed model with machine-labeled annotations achieves great results, with only a 1% difference in accuracy between the machine-labeled annotations and the human-labeled annotations.
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CVPR - Few-Shot Object Recognition from Machine-Labeled Web Images
2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2017Co-Authors: Zhongwen Xu, Yi YangAbstract:With the tremendous advances made by Convolutional Neural Networks (ConvNets) on object recognition, we can now easily obtain adequately reliable machine-labeled annotations easily from predictions by off-the-shelf ConvNets. In this work, we present an abstraction Memory based framework for few-shot learning, building upon machine-labeled image annotations. Our method takes large-scale machine-annotated dataset (e.g., OpenImages) as an external Memory Bank. In the external Memory Bank, the information is stored in the Memory slots in the form of key-value, in which image feature is regarded as the key and the label embedding serves as the value. When queried by the few-shot examples, our model selects visually similar data from the external Memory Bank and writes the useful information obtained from related external data into another Memory Bank, i.e., abstraction Memory. Long Short-Term Memory (LSTM) controllers and attention mechanisms are utilized to guarantee the data written to the abstraction Memory correlates with the query example. The abstraction Memory concentrates information from the external Memory Bank to make the few-shot recognition effective. In the experiments, we first confirm that our model can learn to conduct few-shot object recognition on clean human-labeled data from the ImageNet dataset. Then, we demonstrate that with our model, machine-labeled image annotations are very effective and abundant resources for performing object recognition on novel categories. Experimental results show that our proposed model with machine-labeled annotations achieves great results, with only a 1% difference in accuracy between the machine-labeled annotations and the human-labeled annotations.
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Few-Shot Object Recognition from Machine-Labeled Web Images
arXiv: Computer Vision and Pattern Recognition, 2016Co-Authors: Zhongwen Xu, Yi YangAbstract:With the tremendous advances of Convolutional Neural Networks (ConvNets) on object recognition, we can now obtain reliable enough machine-labeled annotations easily by predictions from off-the-shelf ConvNets. In this work, we present an abstraction Memory based framework for few-shot learning, building upon machine-labeled image annotations. Our method takes some large-scale machine-annotated datasets (e.g., OpenImages) as an external Memory Bank. In the external Memory Bank, the information is stored in the Memory slots with the form of key-value, where image feature is regarded as key and label embedding serves as value. When queried by the few-shot examples, our model selects visually similar data from the external Memory Bank, and writes the useful information obtained from related external data into another Memory Bank, i.e., abstraction Memory. Long Short-Term Memory (LSTM) controllers and attention mechanisms are utilized to guarantee the data written to the abstraction Memory is correlated to the query example. The abstraction Memory concentrates information from the external Memory Bank, so that it makes the few-shot recognition effective. In the experiments, we firstly confirm that our model can learn to conduct few-shot object recognition on clean human-labeled data from ImageNet dataset. Then, we demonstrate that with our model, machine-labeled image annotations are very effective and abundant resources to perform object recognition on novel categories. Experimental results show that our proposed model with machine-labeled annotations achieves great performance, only with a gap of 1% between of the one with human-labeled annotations.