The Experts below are selected from a list of 39924 Experts worldwide ranked by ideXlab platform

Paul H. Siegel - One of the best experts on this subject based on the ideXlab platform.

  • on the capacity of the beta binomial channel model for multi level cell flash memories
    arXiv: Information Theory, 2016
    Co-Authors: Veeresh Taranalli, Hironori Uchikawa, Paul H. Siegel
    Abstract:

    The beta-binomial (BBM) channel model was recently proposed to model the overdispersed statistics of empirically observed bit errors in multi-level cell (MLC) flash memories. In this paper, we study the capacity of the BBM channel model for MLC flash memories. Using the compound channel approach, we first show that the BBM channel model capacity is zero. However, through empirical observation, this appears to be a very pessimistic estimate of the flash Memory channel capacity. We propose a refined channel model called the truncated-support beta-binomial (TS-BBM) channel model and derive its capacity. Using empirical error statistics from 1X-nm and 2Y-nm MLC flash memories, we numerically estimate the TS-BBM channel model capacity as a function of the program/erase (P/E) cycling stress. The capacity of the 2-TS-BBM channel model provides an upper bound on the coding rates for the flash Memory Chip assuming a single binary error correction code is used.

  • On the Capacity of the Beta-Binomial Channel Model for Multi-Level Cell Flash Memories
    IEEE Journal on Selected Areas in Communications, 2016
    Co-Authors: Veeresh Taranalli, Hironori Uchikawa, Paul H. Siegel
    Abstract:

    The beta-binomial (BBM) channel model was recently proposed to model the overdispersed statistics of empirically observed bit errors in multi-level cell (MLC) flash memories. In this paper, we study the capacity of the BBM channel model for MLC flash memories. Using the compound channel approach, we first show that the BBM channel model capacity is zero. However, through empirical observation, this appears to be a very pessimistic estimate of the flash Memory channel capacity. We propose a refined channel model called the truncated-support BBM (TS-BBM) channel model and derive its capacity. Using empirical error statistics from 1X-nm and 2Y-nm MLC flash memories, we numerically estimate the TS-BBM channel model capacity as a function of the program/erase cycling stress. The capacity of the 2-TS-BBM channel model provides an upper bound on the coding rates for the flash Memory Chip assuming a single binary error correction code is used.

Brian R Butcher - One of the best experts on this subject based on the ideXlab platform.

  • magnetoresistive random access Memory using magnetic tunnel junctions
    Proceedings of the IEEE, 2003
    Co-Authors: S Tehrani, M. Durlam, M. Deherrera, J.m. Slaughter, B.n. Engel, Nicholas D Rizzo, J Janesky, J Salter, R W Dave, Brian R Butcher
    Abstract:

    Magnetoresistive random access Memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other Memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the Memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit Memory Chip. Important Memory attributes are compared between MRAM and other Memory technologies.

Veeresh Taranalli - One of the best experts on this subject based on the ideXlab platform.

  • on the capacity of the beta binomial channel model for multi level cell flash memories
    arXiv: Information Theory, 2016
    Co-Authors: Veeresh Taranalli, Hironori Uchikawa, Paul H. Siegel
    Abstract:

    The beta-binomial (BBM) channel model was recently proposed to model the overdispersed statistics of empirically observed bit errors in multi-level cell (MLC) flash memories. In this paper, we study the capacity of the BBM channel model for MLC flash memories. Using the compound channel approach, we first show that the BBM channel model capacity is zero. However, through empirical observation, this appears to be a very pessimistic estimate of the flash Memory channel capacity. We propose a refined channel model called the truncated-support beta-binomial (TS-BBM) channel model and derive its capacity. Using empirical error statistics from 1X-nm and 2Y-nm MLC flash memories, we numerically estimate the TS-BBM channel model capacity as a function of the program/erase (P/E) cycling stress. The capacity of the 2-TS-BBM channel model provides an upper bound on the coding rates for the flash Memory Chip assuming a single binary error correction code is used.

  • On the Capacity of the Beta-Binomial Channel Model for Multi-Level Cell Flash Memories
    IEEE Journal on Selected Areas in Communications, 2016
    Co-Authors: Veeresh Taranalli, Hironori Uchikawa, Paul H. Siegel
    Abstract:

    The beta-binomial (BBM) channel model was recently proposed to model the overdispersed statistics of empirically observed bit errors in multi-level cell (MLC) flash memories. In this paper, we study the capacity of the BBM channel model for MLC flash memories. Using the compound channel approach, we first show that the BBM channel model capacity is zero. However, through empirical observation, this appears to be a very pessimistic estimate of the flash Memory channel capacity. We propose a refined channel model called the truncated-support BBM (TS-BBM) channel model and derive its capacity. Using empirical error statistics from 1X-nm and 2Y-nm MLC flash memories, we numerically estimate the TS-BBM channel model capacity as a function of the program/erase cycling stress. The capacity of the 2-TS-BBM channel model provides an upper bound on the coding rates for the flash Memory Chip assuming a single binary error correction code is used.

Zili Shao - One of the best experts on this subject based on the ideXlab platform.

  • A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014
    Co-Authors: Yi Wang, Luis Angel D. Bathen, Zili Shao, Min Huang, Henry C. B. Chan, Nikil D. Dutt
    Abstract:

    The increasing density of NAND flash Memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibit errors. NAND flash Memory is normally used to store the file system metadata and page mapping information. Thus, a broken physical page containing metadata may cause an unintended and severe change in functionality of the entire flash. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multibit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-Chip hierarchy, or hardware implementation of flash Memory Chip. We evaluate Meta-Cure under a real-embedded platform using a variety of I/O traces. The evaluation platform adopts dual ARM Cortex A9 processor cores with 64 Gb NAND flash Memory. We have evaluated the effectiveness of Meta-Cure on the new technology file system file system. Experimental results show that the proposed technique can reduce uncorrectable page errors by 70.38% with less than 7.86% time overhead in comparison with conventional error correction techniques.

  • meta cure a reliability enhancement strategy for metadata in nand flash Memory storage systems
    Design Automation Conference, 2012
    Co-Authors: Luis Angel D. Bathen, Nikil Dutt, Zili Shao
    Abstract:

    The increasing density of NAND flash Memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multi-bit errors. To ensure the functionality and reliability of flash Memory, the pages containing address mapping information and other metadata should be carefully stored in flash Memory. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multi-bit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-Chip hierarchy, or hardware implementation of flash Memory Chip. Experimental results show that the proposed technique can reduce uncorrectable page errors by 92% with less than 1% space overhead in comparison with conventional error correction techniques.

Lanrong Dung - One of the best experts on this subject based on the ideXlab platform.

  • a nand flash Memory controller for sd mmc flash Memory card
    IEEE Transactions on Magnetics, 2007
    Co-Authors: Lanrong Dung
    Abstract:

    In this paper, a novel NAND flash Memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash Memory Chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash Memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash Memory Chip during the card production stage, the function for supporting various kinds of NAND flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash Memory card controller Chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances

  • a nand flash Memory controller for sd mmc flash Memory card
    IEEE Transactions on Magnetics, 2007
    Co-Authors: Lanrong Dung
    Abstract:

    In this paper, a novel NAND flash Memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash Memory Chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash Memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash Memory Chip during the card production stage, the function for supporting various kinds of NAND flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash Memory card controller Chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances