The Experts below are selected from a list of 15855 Experts worldwide ranked by ideXlab platform
Akihiro Nakao - One of the best experts on this subject based on the ideXlab platform.
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data plane Programmability in sdn
International Conference on Network Protocols, 2014Co-Authors: Hamid Farhad, Hyunyong Lee, Akihiro NakaoAbstract:Software-Defined Networking (SDN) research, from the beginning, focuses more on the development and Programmability of the control plane. In this paper, first we posit that we need data plane focused research in addition to control plane for SDN. Then, we review data plane related contributions in SDN to indicate there is a gap that need to be considered from the community. Next, we review some existing technologies that can be used to realize a software-centric SDN data plane compared with the current hardware-centric proposals. Finally, we discuss challenges and directions for the community as the future steps in SDN data plane development.
Peter Han Joo Chong - One of the best experts on this subject based on the ideXlab platform.
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delay efficient software defined networking based architecture for vehicular networks
International Conference on Conceptual Structures, 2016Co-Authors: K Kushan L Sudheera, G Md Nawaz G Ali, Peter Han Joo ChongAbstract:Vehicular ad-hoc network (VANET) has emerged as a viable solution for network related problems in intelligent transportation system (ITS). However, with its current architecture, VANET has not been able to fulfill some of the necessities of vehicular networks and most importantly still lacking flexibility and Programmability. Recently Software Defined Networking (SDN) has been introduced into the vehicular domain in order to overcome the shortcomings in VANET. Though the introduced Software Defined Vehicular Network (SDVN) architectures provide flexibility and Programmability into the networks with higher packet delivery ratios (PDRs), they have violated the stringent delay requirement in VANET, provoking questions on its usability. So in this paper, we propose a novel SDVN architecture which gives priority to delay requirements in VANET. We have also compared the delay profiles of VANET and other SDVN architectures with our proposed architecture, both theoretically and experimentally.
Hamid Farhad - One of the best experts on this subject based on the ideXlab platform.
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data plane Programmability in sdn
International Conference on Network Protocols, 2014Co-Authors: Hamid Farhad, Hyunyong Lee, Akihiro NakaoAbstract:Software-Defined Networking (SDN) research, from the beginning, focuses more on the development and Programmability of the control plane. In this paper, first we posit that we need data plane focused research in addition to control plane for SDN. Then, we review data plane related contributions in SDN to indicate there is a gap that need to be considered from the community. Next, we review some existing technologies that can be used to realize a software-centric SDN data plane compared with the current hardware-centric proposals. Finally, we discuss challenges and directions for the community as the future steps in SDN data plane development.
Wu-chun Feng - One of the best experts on this subject based on the ideXlab platform.
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Bridging the Performance-Programmability Gap for FPGAs via OpenCL: A Case Study with OpenDwarfs
2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016Co-Authors: Konstantinos Krommydas, Ahmed E. Helal, Anshuman Verma, Wu-chun FengAbstract:For decades, the streaming architecture of FPGAs has delivered accelerated performance across many application domains, such as option pricing solvers in finance, computational fluid dynamics in oil and gas, and packet processing in network routers and firewalls. However, this performance has come at the significant expense of Programmability, i.e., the performance-Programmability gap. In particular, FPGA developers use a hardware design language (HDL) to implement the application data path and to design hardware modules for computation pipelines, memory management, synchronization, and communication. This process requires extensive low-level knowledge of the target FPGA architecture and consumes significant development time and effort. To address this lack of Programmability of FPGAs, OpenCL provides an easy-to-use and portable programming model for CPUs, GPUs, APUs, and now, FPGAs. However, this significantly improved Programmability can come at the expense of performance, that is, there still remains a performance-Programmability gap. To improve the performance of OpenCL kernels on FPGAs, and thus, bridge the performance-Programmability gap, we apply and evaluate the effect of various optimization techniques on GEM, an N-body method from the OpenDwarfs benchmark suite.
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on the Programmability and performance of heterogeneous platforms
International Conference on Parallel and Distributed Systems, 2013Co-Authors: Konstantinos Krommydas, Thomas R W Scogland, Wu-chun FengAbstract:General-purpose computing on an ever-broadening array of parallel devices has led to an increasingly complex and multi-dimensional landscape with respect to Programmability and performance optimization. The growing diversity of parallel architectures presents many challenges to the domain scientist, including device selection, programming model, and level of investment in optimization. All of these choices influence the balance between Programmability and performance. In this paper, we characterize the performance achievable across a range of optimizations, along with their Programmability, for multi- and many-core platforms - specifically, an Intel Sandy Bridge CPU, Intel Xeon Phi co-processor, and NVIDIA Kepler K20 GPU - in the context of an n-body, molecular-modeling application called GEM. Our systematic approach to optimization delivers implementations with speed-ups of 194.98×, 885.18×, and 1020.88× on the CPU, Xeon Phi, and GPU, respectively, over the naive serial version. Beyond the speed-ups, we characterize the incremental optimization of the code from naive serial to fully hand-tuned on each platform through four distinct phases of increasing complexity to expose the strengths and weaknesses of the programming models offered by each platform.
Mark J Bull - One of the best experts on this subject based on the ideXlab platform.
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ipregel vertex centric Programmability vs memory efficiency and performance why choose
arXiv: Distributed Parallel and Cluster Computing, 2020Co-Authors: Ludovic Anthony Richard Capelli, Timothy A K Zakian, Nick Brown, Mark J BullAbstract:The vertex-centric programming model, designed to improve the Programmability in graph processing application writing, has attracted great attention over the years. However, shared memory frameworks that implement the vertex-centric interface all expose a common tradeoff: Programmability against memory efficiency and performance. Our approach, iPregel, preserves vertex-centric Programmability, while implementing optimisations for performance, and designing these so they are transparent to a user's application code, hence not impacting Programmability. In this paper, we evaluate iPregel against FemtoGraph, whose characteristics are identical, an asynchronous counterpart GraphChi and the vertex-subset-centric framework Ligra. Our experiments include three of the most popular vertex-centric benchmark applications over 4 real-world publicly accessible graphs, which cover orders of magnitude between a million to a billion edges, measuring execution time and peak memory usage. Finally, we evaluate the Programmability of each framework by comparing against Google's original Pregel framework. Experiments demonstrate that iPregel, like FemtoGraph, does not sacrifice vertex-centric Programmability for additional performance and memory efficiency optimisations, which contrasts against GraphChi and Ligra. Sacrificing vertex-centric Programmability allowed the latter to benefit from substantial performance and memory efficiency gains. We demonstrate that iPregel is up to 2300 times faster than FemtoGraph, as well as generating a memory footprint up to 100 times smaller. Ligra and GraphChi are up to 17000 and 700 times faster than FemtoGraph but, when comparing against iPregel, this maximum speed-up drops to 10. Furthermore, with PageRank, iPregel is the fastest overall. For memory efficiency, iPregel provides the same memory efficiency as Ligra and 3 to 6 times lighter than GraphChi on average.
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ipregel vertex centric Programmability vs memory efficiency and performance why choose
Parallel Computing, 2019Co-Authors: Ludovic Anthony Richard Capelli, Timothy A K Zakian, Nick Brown, Mark J BullAbstract:Abstract The vertex-centric programming model, designed to improve the Programmability in graph processing application writing, has attracted great attention over the years. Multiple shared memory frameworks that have implemented the vertex-centric interface all expose a common tradeoff: Programmability against memory efficiency and performance. Our approach consists in preserving vertex-centric Programmability, while implementing optimisations missing from FemtoGraph, developing new ones and designing these so they are transparent to a user’s application code, hence not impacting Programmability. We therefore implemented our own shared memory vertex-centric framework iPregel, relying on in-memory storage and synchronous execution. In this paper, we evaluate it against FemtoGraph, whose characteristics are identical, but also an asynchronous counterpart GraphChi and the vertex-subset-centric framework Ligra. Our experiments include three of the most popular vertex-centric benchmark applications over 4 real-world publicly accessible graphs, which cover all orders of magnitude between a million to a billion edges. We then measure the execution time and the peak memory usage. Finally, we evaluate the Programmability of each framework by comparing it against the original Pregel, Google’s closed-source implementation that started the whole area of vertex-centric programming. Experiments demonstrate that iPregel, like FemtoGraph, does not sacrifice vertex-centric Programmability for additional performance and memory efficiency optimisations, which contrasts with GraphChi and Ligra. Sacrificing vertex-centric Programmability allowed the latter to benefit from substantial performance and memory efficiency gains. However, experiments demonstrate that iPregel is up to 2300 times faster than FemtoGraph, as well as generating a memory footprint up to 100 times smaller. These results greatly change the situation; Ligra and GraphChi are up to 17,000 and 700 times faster than FemtoGraph but, when comparing against iPregel, this maximum speed-up drops to 10. Furthermore, on PageRank, it is iPregel that proves to be the fastest overall. When it comes to memory efficiency, the same observation applies; Ligra and GraphChi are 100 and 50 times lighter than FemtoGraph, but iPregel nullifies these benefits: it provides the same memory efficiency as Ligra and even proves to be 3 to 6 times lighter than GraphChi on average. In other words, iPregel demonstrates that preserving vertex-centric Programmability is not incompatible with a competitive performance and memory efficiency.
