The Experts below are selected from a list of 20280 Experts worldwide ranked by ideXlab platform
Vijay Nagarajan - One of the best experts on this subject based on the ideXlab platform.
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a primer on Memory Consistency and cache coherence second edition
2020Co-Authors: Vijay Nagarajan, Daniel J Sorin, Mark D Hill, David A WoodAbstract:Abstract Many modern computer systems, including homogeneous and heterogeneous architectures, support shared Memory in hardware. In a shared Memory system, each of the processor cores may read and ...
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verification of a lazy cache coherence protocol against a weak Memory model
arXiv: Logic in Computer Science, 2017Co-Authors: Christopher J Banks, Marco Elver, Ruth Hoffmann, Susmit Sarkar, Paul B Jackson, Vijay NagarajanAbstract:In this paper we verify a modern lazy cache coherence protocol, TSO-CC, against the Memory Consistency model it was designed for, TSO. We achieve this by first showing a weak simulation relation between TSO-CC (with a fixed number of processors) and a novel finite-state operational model which exhibits the laziness of TSO-CC and satisfies TSO. We then extend this by an existing parameterisation technique, allowing verification for an unlimited number of processors. The approach is executed entirely within a model checker, no external tool is required and very little in-depth knowledge of formal verification methods is required of the verifier.
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mcversi a test generation framework for fast Memory Consistency verification in simulation
High-Performance Computer Architecture, 2016Co-Authors: Vijay Nagarajan, Marco ElverAbstract:The Memory Consistency model (MCM), which formally specifies the behaviour of the Memory system, is used by programmers to reason about parallel programs. It is imperative that hardware adheres to the promised MCM. For this reason, hardware designs must be verified against the specified MCM. One common way to do this is via executing tests, where specific threads of instruction sequences are generated and their executions are checked for adherence to the MCM. It would be extremely beneficial to execute such tests under simulation, i.e. when the functional design implementation of the hardware is being prototyped. Most prior verification methodologies, however, target post-silicon environments, which when applied under simulation would be too slow. We propose McVerSi, a test generation framework for fast MCM verification of a full-system design implementation under simulation. Our primary contribution is a Genetic Programming (GP) based approach to MCM test generation, which relies on a novel crossover function that prioritizes Memory operations contributing to non-determinism, thereby increasing the probability of uncovering MCM bugs. To guide tests towards exercising as much logic as possible, the simulator's reported coverage is used as the fitness function. Furthermore, we increase test throughput by making the test workload simulation-aware. We evaluate our proposed framework using the Gem5 cycle accurate simulator in full-system mode with Ruby. We discover 2 new bugs due to the faulty interaction of the pipeline and the cache coherence protocol. Crucially, these bugs would not have been discovered through individual verification of the pipeline or the coherence protocol. We study 11 bugs in total. Our GP-based test generation approach finds all bugs consistently, therefore providing much higher guarantees compared to alternative approaches (pseudo-random test generation and litmus tests).
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rc3 Consistency directed cache coherence for x86 64 with rc extensions
International Conference on Parallel Architectures and Compilation Techniques, 2015Co-Authors: Marco Elver, Vijay NagarajanAbstract:The recent convergence towards programming language based Memory Consistency models has sparked renewed interest in lazy cache coherence protocols. These protocols exploit synchronization information by enforcing coherence only at synchronization boundaries via self-invalidation. In effect, such protocols do not require sharer tracking which benefits scalability. On the downside, such protocols are only readily applicable to a restricted set of Consistency models, such as Release Consistency (RC), which expose synchronization information explicitly. In particular, existing architectures with stricter Consistency models (such as x86-64) cannot readily make use of lazy coherence protocols without either: changing the architecture's Consistency model to (a variant of) RC at the expense of backwards compatibility, or adapting the protocol to satisfy the stricter Consistency model, thereby failing to benefit from synchronization information. We show an approach for the x86-64 architecture, which is a compromise between the two. First, we propose a mechanism to convey synchronization information via a simple ISA extension, while retaining backwards compatibility with legacy codes and older microarchitectures. Second, we propose RC3, a scalable hardware cache coherence protocol for RCtso, the resulting Memory Consistency model. RC3 does not track sharers, and relies on self-invalidation on acquires. To satisfy RCtso efficiently, the protocol reduces self-invalidations transitively using per-L1 timestamps only. RC3 outperforms a conventional lazy RC protocol by 12%, achieving performance comparable to a MESI directory protocol for RC optimized programs. RC3's storage overhead per cache line scales logarithmically with increasing core count, and reduces on-chip coherence storage overheads by 45% compared to a related approach specifically targeting TSO.
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tso cc Consistency directed cache coherence for tso
High-Performance Computer Architecture, 2014Co-Authors: Marco Elver, Vijay NagarajanAbstract:Traditional directory coherence protocols are designed for the strictest Consistency model, sequential Consistency (SC). When they are used for chip multiprocessors (CMPs) that support relaxed Memory Consistency models, such protocols turn out to be unnecessarily strict. Usually this comes at the cost of scalability (in terms of per core storage), which poses a problem with increasing number of cores in today's CMPs, most of which no longer are sequentially consistent. Because of the wide adoption of Total Store Order (TSO) and its variants in x86 and SPARC processors, and existing parallel programs written for these architectures, we propose TSO-CC, a cache coherence protocol for the TSO Memory Consistency model. TSO-CC does not track sharers, and instead relies on self-invalidation and detection of potential acquires using timestamps to satisfy the TSO Memory Consistency model lazily. Our results show that TSO-CC achieves average performance comparable to a MESI directory protocol, while TSO-CC's storage overhead per cache line scales logarithmically with increasing core count.
Toshiyuki Maeda - One of the best experts on this subject based on the ideXlab platform.
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A general model checking framework for various Memory Consistency models
International Journal on Software Tools for Technology Transfer, 2017Co-Authors: Toshiyuki MaedaAbstract:Relaxed Memory Consistency models are common and essential when multiple processes share a single global address space, such as when using multicore CPUs, distributed shared-Memory programming languages, and so forth. Programming within these models is difficult and error prone, because of non-intuitive behaviors that could not occur in a strict Consistency model. In addition, because the Memory Consistency models vary from language to language, and CPU to CPU, a program that may work correctly on one system may not work on another. To address the problem, this paper describes a model checking framework in which users are able to check their programs under various Memory Consistency models. More specifically, our framework provides a base model that exhibits very relaxed behaviors, and users are able to define various Consistency models by adding constraints to the base model. This paper also describes McSPIN, a prototype implementation of a model checker based on the proposed framework. McSPIN can take a Memory Consistency model as an input, as well as a program and a property to be checked. We have specified the necessary constraints for three practical existing Memory Consistency models (Unified Parallel C, Coarray Fortran, and Itanium). McSPIN verified some example programs correctly, and confirmed the expected differences among the three models.
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observation based concurrent program logic for relaxed Memory Consistency models
Asian Symposium on Programming Languages and Systems, 2016Co-Authors: Tatsuya Abe, Toshiyuki MaedaAbstract:Concurrent program logics are frameworks for constructing proofs, which ensure that concurrent programs work correctly. However, most conventional concurrent program logics do not consider the complexities of modern Memory structures, and the proofs in the logics do not ensure that programs will work correctly. To the best of our knowledge, Independent Reads Independent Writes (IRIW), which is known to have non-intuitive behavior under relaxed Memory Consistency models, has not been fully studied under the context of concurrent program logics. One reason is the gap between theoretical Memory Consistency models that program logics can handle and the realistic Memory Consistency models adopted by actual computer architectures. In this paper, we propose observation variables and invariants that fill this gap, releasing us from the need to construct operational semantics and logic for each specific Memory Consistency model. We describe general operational semantics for relaxed Memory Consistency models, define concurrent program logic sound to the operational semantics, show that observation invariants can be formalized as axioms of the logic, and verify IRIW under an observation invariant. We also obtain a novel insight through constructing the logic. To define logic that is sound to the operational semantics, we dismiss shared variables in programs from assertion languages, and adopt variables observed by threads. This suggests that the so-called bird’s-eye view of the whole computing system disturbs the soundness of the logic.
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A General Model Checking Framework for Various Memory Consistency Models
2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014Co-Authors: Toshiyuki MaedaAbstract:Relaxed Memory Consistency models are common and essential when multiple processes share a single global address space, such as when using multicore CPUs, partitioned global address space languages, and so forth. Programming within these models is difficult and error prone, because of non-intuitive behaviors that could not occur in a sequential Memory Consistency model. In addition, because the Memory Consistency models vary from language to language, and CPU to CPU, a program which may work correctly on one system may not work on another. To address the problem, this paper describes a model checking framework in which users are able to check their programs under various Memory Consistency models. More specifically, our framework provides a base model that exhibits very relaxed behaviors, and users are able to define various Consistency models by adding constraints to the base model. This paper also describes a prototype implementation of a model checker based on the proposed framework. We have specified the necessary constraints for three practical existing Memory Consistency models (UPC, Coarray Fortran, and Itanium). Our model checker verified some example programs correctly, and confirmed the expected differences among the three models.
Daniel J Sorin - One of the best experts on this subject based on the ideXlab platform.
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a primer on Memory Consistency and cache coherence second edition
2020Co-Authors: Vijay Nagarajan, Daniel J Sorin, Mark D Hill, David A WoodAbstract:Abstract Many modern computer systems, including homogeneous and heterogeneous architectures, support shared Memory in hardware. In a shared Memory system, each of the processor cores may read and ...
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exploring Memory Consistency for massively threaded throughput oriented processors
International Symposium on Computer Architecture, 2013Co-Authors: Blake A Hechtman, Daniel J SorinAbstract:We re-visit the issue of hardware Consistency models in the new context of massively-threaded throughput-oriented processors (MTTOPs). A prominent example of an MTTOP is a GPGPU, but other examples include Intel's MIC architecture and some recent academic designs. MTTOPs differ from CPUs in many significant ways, including their ability to tolerate latency, their Memory system organization, and the characteristics of the software they run. We compare implementations of various hardware Consistency models for MTTOPs in terms of performance, energy-efficiency, hardware complexity, and programmability. Our results show that the choice of hardware Consistency model has a surprisingly minimal impact on performance and thus the decision should be based on hardware complexity, energy-efficiency, and programmability. For many MTTOPs, it is likely that even a simple implementation of sequential Consistency is attractive.
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a primer on Memory Consistency and cache coherence
2012Co-Authors: Daniel J Sorin, Mark D Hill, David A WoodAbstract:Many modern computer systems and most multicore chips (chip multiprocessors) support shared Memory in hardware. In a shared Memory system, each of the processor cores may read and write to a single shared address space. For a shared Memory machine, the Memory Consistency model defines the architecturally visible behavior of its Memory system. Consistency definitions provide rules about loads and stores (or Memory reads and writes) and how they act upon Memory. As part of supporting a Memory Consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of Consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies
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specifying and dynamically verifying address translation aware Memory Consistency
Architectural Support for Programming Languages and Operating Systems, 2010Co-Authors: Bogdan F Romanescu, Alvin R Lebeck, Daniel J SorinAbstract:Computer systems with virtual Memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear specification of correct behavior. To address this need, we develop a framework for AT-aware Memory Consistency models. We expand and divide Memory Consistency into the physical address Memory Consistency (PAMC) model that defines the behavior of operations on physical addresses and the virtual address Memory Consistency (VAMC) model that defines the behavior of operations on virtual addresses. As part of this expansion, we show what AT features are required to bridge the gap between PAMC and VAMC. Based on our AT-aware Memory Consistency specifications, we design efficient dynamic verification hardware that can detect violations of VAMC and thus detect the effects of design bugs and runtime faults, including most AT related bugs in published errata.
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dynamic verification of Memory Consistency in cache coherent multithreaded computer architectures
IEEE Transactions on Dependable and Secure Computing, 2009Co-Authors: Albert Meixner, Daniel J SorinAbstract:Multithreaded servers with cache-coherent shared Memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recovery. Correct operation of the Memory system is defined by the Memory Consistency model. Errors can therefore be detected by checking if the observed Memory system behavior deviates from the specified Consistency model. Based on recent work, we design a framework for dynamic verification of Memory Consistency (DVMC). The framework consists of mechanisms to verify three invariants that are proven to guarantee that a specified Memory Consistency model is obeyed. We describe an implementation of the framework for the SPARCv9 architecture, and we experimentally evaluate its performance using full-system simulation of commercial workloads.
Cindy Lustig - One of the best experts on this subject based on the ideXlab platform.
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a ten year follow up of a study of Memory for the attack of september 11 2001 flashbulb memories and memories for flashbulb events
Journal of Experimental Psychology: General, 2015Co-Authors: William Hirst, Robert Meksin, Chandan J Vaidya, Karen J Mitchell, Elizabeth A. Phelps, Andrew E. Budson, Randy L Buckner, Marcia K. Johnson, John D. E. Gabrieli, Cindy LustigAbstract:: Within a week of the attack of September 11, 2001, a consortium of researchers from across the United States distributed a survey asking about the circumstances in which respondents learned of the attack (their flashbulb memories) and the facts about the attack itself (their event memories). Follow-up surveys were distributed 11, 25, and 119 months after the attack. The study, therefore, examines retention of flashbulb memories and event memories at a substantially longer retention interval than any previous study using a test-retest methodology, allowing for the study of such memories over the long term. There was rapid forgetting of both flashbulb and event memories within the first year, but the forgetting curves leveled off after that, not significantly changing even after a 10-year delay. Despite the initial rapid forgetting, confidence remained high throughout the 10-year period. Five putative factors affecting flashbulb Memory Consistency and event Memory accuracy were examined: (a) attention to media, (b) the amount of discussion, (c) residency, (d) personal loss and/or inconvenience, and (e) emotional intensity. After 10 years, none of these factors predicted flashbulb Memory Consistency; media attention and ensuing conversation predicted event Memory accuracy. Inconsistent flashbulb memories were more likely to be repeated rather than corrected over the 10-year period; inaccurate event memories, however, were more likely to be corrected. The findings suggest that even traumatic memories and those implicated in a community's collective identity may be inconsistent over time and these inconsistencies can persist without the corrective force of external influences.
Lustig Cindy - One of the best experts on this subject based on the ideXlab platform.
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A Ten-Year Follow-Up of a Study of Memory for the Attack of September 11, 2001: Flashbulb Memories and Memories for Flashbulb Events.
Journal of Experimental Psychology: General, 2015Co-Authors: Hirst William, John D. E. Gabrieli, Phelps, Elizabeth A, Meksin Robert, Vaidya, Chandan J, Johnson, Marcia K, Mitchell, Karen J, Buckner, Randy L, Budson, Andrew E, Lustig CindyAbstract:Within a week of the attack of September 11, 2001, a consortium of researchers from across the United States distributed a survey asking about the circumstances in which respondents learned of the attack (their flashbulb memories) and the facts about the attack itself (their event memories). Follow-up surveys were distributed 11, 25, and 119 months after the attack. The study, therefore, examines retention of flashbulb memories and event memories at a substantially longer retention interval than any previous study using a test–retest methodology, allowing for the study of such memories over the long term. There was rapid forgetting of both flashbulb and event memories within the first year, but the forgetting curves leveled off after that, not significantly changing even after a 10-year delay. Despite the initial rapid forgetting, confidence remained high throughout the 10-year period. Five putative factors affecting flashbulb Memory Consistency and event Memory accuracy were examined: (a) attention to media, (b) the amount of discussion, (c) residency, (d) personal loss and/or inconvenience, and (e) emotional intensity. After 10 years, none of these factors predicted flashbulb Memory Consistency; media attention and ensuing conversation predicted event Memory accuracy. Inconsistent flashbulb memories were more likely to be repeated rather than corrected over the 10-year period; inaccurate event memories, however, were more likely to be corrected. The findings suggest that even traumatic memories and those implicated in a community’s collective identity may be inconsistent over time and these inconsistencies can persist without the corrective force of external influences.This is the author accepted manuscript. The final version is available from the American Psychological Association via http://dx.doi.org/10.1037/xge000005
