The Experts below are selected from a list of 9192 Experts worldwide ranked by ideXlab platform
Bengt Jonsson - One of the best experts on this subject based on the ideXlab platform.
-
a skiplist based concurrent priority queue with minimal Memory Contention
International Conference on Principles of Distributed Systems, 2013Co-Authors: Jonatan Linden, Bengt JonssonAbstract:Priority queues are fundamental to many multiprocessor applications. Several priority queue algorithms based on skiplists have been proposed, as skiplists allow concurrent accesses to different parts of the data structure in a simple way. However, for priority queues on multiprocessors, an inherent bottleneck is the operation that deletes the minimal element. We present a linearizable, lock-free, concurrent priority queue algorithm, based on skiplists, which minimizes the Contention for shared Memory that is caused by the DeleteMin operation. The main idea is to minimize the number of global updates to shared Memory that are performed in one DeleteMin. In comparison with other skiplist-based priority queue algorithms, our algorithm achieves a 30 - 80% improvement.
-
OPODIS - A Skiplist-Based Concurrent Priority Queue with Minimal Memory Contention
Lecture Notes in Computer Science, 2013Co-Authors: Jonatan Linden, Bengt JonssonAbstract:Priority queues are fundamental to many multiprocessor applications. Several priority queue algorithms based on skiplists have been proposed, as skiplists allow concurrent accesses to different parts of the data structure in a simple way. However, for priority queues on multiprocessors, an inherent bottleneck is the operation that deletes the minimal element. We present a linearizable, lock-free, concurrent priority queue algorithm, based on skiplists, which minimizes the Contention for shared Memory that is caused by the DeleteMin operation. The main idea is to minimize the number of global updates to shared Memory that are performed in one DeleteMin. In comparison with other skiplist-based priority queue algorithms, our algorithm achieves a 30 - 80% improvement.
Jonatan Linden - One of the best experts on this subject based on the ideXlab platform.
-
a skiplist based concurrent priority queue with minimal Memory Contention
International Conference on Principles of Distributed Systems, 2013Co-Authors: Jonatan Linden, Bengt JonssonAbstract:Priority queues are fundamental to many multiprocessor applications. Several priority queue algorithms based on skiplists have been proposed, as skiplists allow concurrent accesses to different parts of the data structure in a simple way. However, for priority queues on multiprocessors, an inherent bottleneck is the operation that deletes the minimal element. We present a linearizable, lock-free, concurrent priority queue algorithm, based on skiplists, which minimizes the Contention for shared Memory that is caused by the DeleteMin operation. The main idea is to minimize the number of global updates to shared Memory that are performed in one DeleteMin. In comparison with other skiplist-based priority queue algorithms, our algorithm achieves a 30 - 80% improvement.
-
OPODIS - A Skiplist-Based Concurrent Priority Queue with Minimal Memory Contention
Lecture Notes in Computer Science, 2013Co-Authors: Jonatan Linden, Bengt JonssonAbstract:Priority queues are fundamental to many multiprocessor applications. Several priority queue algorithms based on skiplists have been proposed, as skiplists allow concurrent accesses to different parts of the data structure in a simple way. However, for priority queues on multiprocessors, an inherent bottleneck is the operation that deletes the minimal element. We present a linearizable, lock-free, concurrent priority queue algorithm, based on skiplists, which minimizes the Contention for shared Memory that is caused by the DeleteMin operation. The main idea is to minimize the number of global updates to shared Memory that are performed in one DeleteMin. In comparison with other skiplist-based priority queue algorithms, our algorithm achieves a 30 - 80% improvement.
Yong Meng Teo - One of the best experts on this subject based on the ideXlab platform.
-
MASCOTS - Modeling the Energy-Time Performance of MIC Architecture System
2016 IEEE 24th International Symposium on Modeling Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2016Co-Authors: Lavanya Ramapantulu, Thy Dao, Dumitrel Loghin, Nam Thoai, Yong Meng TeoAbstract:Many Integrated Core (MIC) architecture systems are becoming increasingly popular for HPC applications as they have the dual-advantage of accelerating vector processing and a general-purpose programming model. One of the key challenges for energy-efficient execution on MIC architecture systems is to determine time and energy-efficient configurations among a large system configuration space. Given a parallel program with an execution time deadline and an energy budget, we propose a measurement-based analytical modeling approach to determine these system configurations. In contrast to current approaches, we model both inter-and intra-core resource overlaps, Memory Contention among threads within a core and Memory Contention across multiple cores. The model is validated against direct measurement using six representative HPC applications on Intel Xeon Phi system. We show that a Pareto frontier consisting of optimal configurations exist for a parallel program executing on MIC architecture systems. To further understand the Pareto frontier, we use the performance-to-power ratio metric (PPR), that quantifies the amount of useful computations performed per unit energy during the execution. The proposed approach can be used to determine what thread affinity is suitable for offloading execution to accelerators such as Xeon Phi and save energy.
-
understanding off chip Memory Contention of parallel programs in multicore systems
International Conference on Parallel Processing, 2011Co-Authors: Bogdan Marius Tudor, Yong Meng Teo, Simon SeeAbstract:Memory Contention is an important performance issue in current multicore architectures. In this paper, we focus on understanding how off-chip Memory Contention affects the performance of parallel applications. Using measurements conducted on state-of-the-art multicore systems, we observed that off-chip Memory traffic is not always bursty, as it was previously reported in literature. Burstiness depends on the problem size. Small problem sizes lead to bursty Memory traffic, and generate small off-chip Contention. In contrast, when large program sizes cause Memory Contention, the Memory traffic is non-bursty. Based on these observations, we propose an analytical model that relates the growth of Memory Contention to the number of active cores and to the problem size, for both uniform (UMA) and non-uniform Memory access (NUMA) systems. Our model differs from measurements on average by less than 14\%. Contention for off-chip Memory grows exponentially with the number of active cores, but adding additional Memory controllers reduces the Memory Contention. For programs such as the penta diagonal solver SP from NPB benchmark, with a large matrix of $162^3$ elements (input size C), our analysis shows that Memory Contention increases the total number of processor cycles to execute the program by more than ten times on a machine with 24 cores.
-
ICPP - Understanding Off-Chip Memory Contention of Parallel Programs in Multicore Systems
2011 International Conference on Parallel Processing, 2011Co-Authors: Bogdan Marius Tudor, Yong Meng Teo, Simon SeeAbstract:Memory Contention is an important performance issue in current multicore architectures. In this paper, we focus on understanding how off-chip Memory Contention affects the performance of parallel applications. Using measurements conducted on state-of-the-art multicore systems, we observed that off-chip Memory traffic is not always bursty, as it was previously reported in literature. Burstiness depends on the problem size. Small problem sizes lead to bursty Memory traffic, and generate small off-chip Contention. In contrast, when large program sizes cause Memory Contention, the Memory traffic is non-bursty. Based on these observations, we propose an analytical model that relates the growth of Memory Contention to the number of active cores and to the problem size, for both uniform (UMA) and non-uniform Memory access (NUMA) systems. Our model differs from measurements on average by less than 14\%. Contention for off-chip Memory grows exponentially with the number of active cores, but adding additional Memory controllers reduces the Memory Contention. For programs such as the penta diagonal solver SP from NPB benchmark, with a large matrix of $162^3$ elements (input size C), our analysis shows that Memory Contention increases the total number of processor cycles to execute the program by more than ten times on a machine with 24 cores.
-
IPDPS - A Practical Approach for Performance Analysis of Shared-Memory Programs
2011 IEEE International Parallel & Distributed Processing Symposium, 2011Co-Authors: Bogdan Marius Tudor, Yong Meng TeoAbstract:Parallel programming has transcended from HPC into mainstream, enabled by a growing number of programming models, languages and methodologies, as well as the availability of multicore systems. However, performance analysis of parallel programs is still difficult, especially for large and complex programs, or applications developed using different programming models. This paper proposes a simple analytical model for studying the speedup of shared-Memory programs on multicore systems. The proposed model derives the speedup and speedup loss from data dependency and Memory overhead for various configurations of threads, cores and Memory access policies in UMA and NUMA systems. The model is practical because it uses only generally available and non-intrusive inputs derived from the trace of the operating system run-queue and hardware events counters. Using six OpenMP HPC dwarfs from the NPB benchmark, our model differs from measurement results on average by 9% for UMA and 11% on NUMA. Our analysis shows that speedup loss is dominated by Memory Contention, especially for larger problem sizes. For the worst performing structured grid dwarf on UMA, Memory Contention accounts for up to 99% of the speedup loss. Based on this insight, we apply our model to determine the optimal number of cores that alleviates Memory Contention, maximizing speedup and reducing execution time.
Gilles Muller - One of the best experts on this subject based on the ideXlab platform.
-
Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System
2016Co-Authors: Antoine Blin, Julia Lawall, Cedric Courtaud, Julien Sopena, Gilles MullerAbstract:Complex embedded systems today commonly involve a mix of real-time and best-effort applications. The recent emergence of small low-cost commodity UMA multicore processors raises the possibility of running both kinds of applications on a single machine, with virtualization ensuring that the best-effort applications cannot steal CPU cycles from the real-time applications. Nevertheless, Memory Contention can introduce other sources of delay, that can lead to missed deadlines. In this research report, we present a combined offline/online Memory bandwidth monitoring approach. Our approach estimates and limits the impact of the Memory Contention incurred by the best-effort applications on the execution time of the real-time application. We show that our approach is compatible with the hardware counters provided by current small commodity multicore processors. Using our approach, the system designer can limit the overhead on the real-time application to under 5% of its expected execution time, while still enabling progress of the best-effort applications.
-
ECRTS - Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System
2016 28th Euromicro Conference on Real-Time Systems (ECRTS), 2016Co-Authors: Antoine Blin, Julia Lawall, Cedric Courtaud, Julien Sopena, Gilles MullerAbstract:Complex embedded systems today commonly involve a mix of real-time and best-effort applications. The recent emergence of low-cost multicore processors raises the possibility of running both kinds of applications on a single machine, with virtualization ensuring isolation. Nevertheless, Memory Contention can introduce other sources of delay, that can lead to missed deadlines. In this paper, we present a combined offline/online Memory bandwidth monitoring approach. Our approach estimates and limits the impact of the Memory Contention incurred by the best-effort applications on the execution time of the real-time application. We show that our approach is compatible with the hardware counters provided by current small commodity multicore processors. Using our approach, the system designer can limit the overhead on the real-time application to under 5% of its expected execution time, while still enabling progress of the best-effort applications.
-
Scheduling support for transactional Memory Contention management
2010Co-Authors: Walther Maldonado, Patrick Marlier, Pascal Felber, Julia Lawall, Adi Suissa, Danny Hendler, Alexandra Fedorova, Gilles MullerAbstract:Transactional Memory (TM) is considered as one of the most promising paradigms for developing concurrent applications. TM has been shown to scale well on multiple cores when the data access pattern behaves "well," i.e., when few conflicts are induced. In contrast, data patterns with frequent write sharing, with long transactions, or when many threads contend for a smaller number of cores, result in numerous conflicts. Until recently, TM implementations had little control of transactional threads, which remained under the supervision of the kernel's transaction-ignorant scheduler. Conflicts are thus traditionally resolved by consulting an STM-level Contention manager. Consequently, the Contention managers of these "conventional" TM implementations suffer from a lack of precision and often fail to ensure reasonable performance in high-Contention workloads. Recently, scheduling-based TM Contention-management has been proposed for increasing TM efficiency under high-Contention [2, 5, 19]. However, only user-level schedulers have been considered. In this work, we propose, implement and evaluate several novel kernel-level scheduling support mechanisms for TM Contention management. We also investigate different strategies for efficient communication between the kernel and the user-level TM library. To the best of our knowledge, our work is the first to investigate kernel-level support for TM Contention management. We have introduced kernel-level TM scheduling support into both the Linux and Solaris kernels. Our experimental evaluation demonstrates that lightweight kernel-level scheduling support significantly reduces the number of aborts while improving transaction throughput on various workloads.
-
PPOPP - Scheduling support for transactional Memory Contention management
Proceedings of the 15th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '10, 2010Co-Authors: Walther Maldonado, Patrick Marlier, Pascal Felber, Julia Lawall, Adi Suissa, Danny Hendler, Alexandra Fedorova, Gilles MullerAbstract:Transactional Memory (TM) is considered as one of the most promising paradigms for developing concurrent applications. TM has been shown to scale well on >multiple cores when the data access pattern behaves "well," i.e., when few conflicts are induced. In contrast, data patterns with frequent write sharing, with long transactions, or when many threads contend for a smaller number of cores, result in numerous conflicts. Until recently, TM implementations had little control of transactional threads, which remained under the supervision of the kernel's transaction-ignorant scheduler. Conflicts are thus traditionally resolved by consulting an STM-level Contention manager. Consequently, the Contention managers of these "conventional" TM implementations suffer from a lack of precision and often fail to ensure reasonable performance in high-Contention workloads. Recently, scheduling-based TM Contention-management has been proposed for increasing TM efficiency under high-Contention [2, 5, 19]. However, only user-level schedulers have been considered. In this work, we propose, implement and evaluate several novel kernel-level scheduling support mechanisms for TM Contention management. We also investigate different strategies for efficient communication between the kernel and the user-level TM library. To the best of our knowledge, our work is the first to investigate kernel-level support for TM Contention management. We have introduced kernel-level TM scheduling support into both the Linux and Solaris kernels. Our experimental evaluation demonstrates that lightweight kernel-level scheduling support significantly reduces the number of aborts while improving transaction throughput on various workloads.
Bogdan Marius Tudor - One of the best experts on this subject based on the ideXlab platform.
-
understanding off chip Memory Contention of parallel programs in multicore systems
International Conference on Parallel Processing, 2011Co-Authors: Bogdan Marius Tudor, Yong Meng Teo, Simon SeeAbstract:Memory Contention is an important performance issue in current multicore architectures. In this paper, we focus on understanding how off-chip Memory Contention affects the performance of parallel applications. Using measurements conducted on state-of-the-art multicore systems, we observed that off-chip Memory traffic is not always bursty, as it was previously reported in literature. Burstiness depends on the problem size. Small problem sizes lead to bursty Memory traffic, and generate small off-chip Contention. In contrast, when large program sizes cause Memory Contention, the Memory traffic is non-bursty. Based on these observations, we propose an analytical model that relates the growth of Memory Contention to the number of active cores and to the problem size, for both uniform (UMA) and non-uniform Memory access (NUMA) systems. Our model differs from measurements on average by less than 14\%. Contention for off-chip Memory grows exponentially with the number of active cores, but adding additional Memory controllers reduces the Memory Contention. For programs such as the penta diagonal solver SP from NPB benchmark, with a large matrix of $162^3$ elements (input size C), our analysis shows that Memory Contention increases the total number of processor cycles to execute the program by more than ten times on a machine with 24 cores.
-
ICPP - Understanding Off-Chip Memory Contention of Parallel Programs in Multicore Systems
2011 International Conference on Parallel Processing, 2011Co-Authors: Bogdan Marius Tudor, Yong Meng Teo, Simon SeeAbstract:Memory Contention is an important performance issue in current multicore architectures. In this paper, we focus on understanding how off-chip Memory Contention affects the performance of parallel applications. Using measurements conducted on state-of-the-art multicore systems, we observed that off-chip Memory traffic is not always bursty, as it was previously reported in literature. Burstiness depends on the problem size. Small problem sizes lead to bursty Memory traffic, and generate small off-chip Contention. In contrast, when large program sizes cause Memory Contention, the Memory traffic is non-bursty. Based on these observations, we propose an analytical model that relates the growth of Memory Contention to the number of active cores and to the problem size, for both uniform (UMA) and non-uniform Memory access (NUMA) systems. Our model differs from measurements on average by less than 14\%. Contention for off-chip Memory grows exponentially with the number of active cores, but adding additional Memory controllers reduces the Memory Contention. For programs such as the penta diagonal solver SP from NPB benchmark, with a large matrix of $162^3$ elements (input size C), our analysis shows that Memory Contention increases the total number of processor cycles to execute the program by more than ten times on a machine with 24 cores.
-
IPDPS - A Practical Approach for Performance Analysis of Shared-Memory Programs
2011 IEEE International Parallel & Distributed Processing Symposium, 2011Co-Authors: Bogdan Marius Tudor, Yong Meng TeoAbstract:Parallel programming has transcended from HPC into mainstream, enabled by a growing number of programming models, languages and methodologies, as well as the availability of multicore systems. However, performance analysis of parallel programs is still difficult, especially for large and complex programs, or applications developed using different programming models. This paper proposes a simple analytical model for studying the speedup of shared-Memory programs on multicore systems. The proposed model derives the speedup and speedup loss from data dependency and Memory overhead for various configurations of threads, cores and Memory access policies in UMA and NUMA systems. The model is practical because it uses only generally available and non-intrusive inputs derived from the trace of the operating system run-queue and hardware events counters. Using six OpenMP HPC dwarfs from the NPB benchmark, our model differs from measurement results on average by 9% for UMA and 11% on NUMA. Our analysis shows that speedup loss is dominated by Memory Contention, especially for larger problem sizes. For the worst performing structured grid dwarf on UMA, Memory Contention accounts for up to 99% of the speedup loss. Based on this insight, we apply our model to determine the optimal number of cores that alleviates Memory Contention, maximizing speedup and reducing execution time.
-
A Practical Approach for Performance Analysis of
2011Co-Authors: Shared-memory Programs, Bogdan Marius Tudor, Yong MengAbstract:Parallel programming has transcended from HPC into mainstream, enabled by a growing number of programming models, languages and methodologies, as well as the availability of multicore systems. However, performance analysis of parallel pro- grams is still difficult, especially for large and complex programs, or applications developed using different programming models. This paper proposes a simple analytical model for studying the speedup of shared-Memory programs on multicore systems. The proposed model derives the speedup and speedup loss from data dependency and Memory overhead for various configurations of threads, cores and Memory access policies in UMA and NUMA systems. The model is practical because it uses only generally available and non-intrusive inputs derived from the trace of the operating system run-queue and hardware events counters. Using six OpenMP HPC dwarfs from the NPB benchmark, our model differs from measurement results on average by 9% for UMA and 11% on NUMA. Our analysis shows that speedup loss is dominated by Memory Contention, especially for larger problem sizes. For the worst performing structured grid dwarf on UMA, Memory Contention accounts for up to 99% of the speedup loss. Based on this insight, we apply our model to determine the optimal number of cores that alleviates Memory Contention, maximizing speedup and reducing execution time.