The Experts below are selected from a list of 3648 Experts worldwide ranked by ideXlab platform

Dominique Ginhac - One of the best experts on this subject based on the ideXlab platform.

  • A 1.3 megapixel FPGA-based smart camera for high dynamic range real time video A 1.3 megapixel FPGA-based smart camera for high dynamic range real time video
    2020
    Co-Authors: Pierre Jean Lapray, Barthélémy Heyrman, Dominique Ginhac, Matthieu Rosse
    Abstract:

    Abstract-A camera is able to capture only a part of a high dynamic range scene information. The same scene can be fully perceived by the human visual system. This is true especially for real scenes where the difference in light intensity between the dark areas and bright areas is high. The imaging technique which can overcome this problem is called HDR (High Dynamic Range). It produces images from a set of multiple LDR images (Low Dynamic Range), captured with different exposure times. This technique appears as one of the most appropriate and a cheap solution to enhance the dynamic range of captured environments. We developed an FPGA-based smart camera that produces a HDR live video colour stream from three successive acquisitions. Our hardware platform is build around a standard LDR CMOS sensor and a Virtex 6 FPGA board. The hardware architecture embeds a multiple exposure control, a memory management unit, the HDR creating, and the tone mapping. Our video camera enables a real-time video at 60 frames per second for a full sensor resolution of 1, 280 × 1, 024 pixels

  • hdr artist an adaptive real time smart camera for high dynamic range imaging
    Journal of Real-time Image Processing, 2016
    Co-Authors: Pierre Jean Lapray, Barthélémy Heyrman, Dominique Ginhac
    Abstract:

    This paper describes a complete FPGA-based smart camera architecture named HDR-ARtiSt (High Dynamic Range Adaptive Real-time Smart camera) which produces a real-time high dynamic range (HDR) live video stream from multiple captures. A specific memory management unit has been defined to adjust the number of acquisitions to improve HDR quality. This smart camera is built around a standard B&W CMOS image sensor and a Xilinx FPGA. It embeds multiple captures, HDR processing, data display and transfer, which is an original contribution compared to the state-of-the-art. The proposed architecture enables a real-time HDR video flow for a full sensor resolution (1.3 Mega pixels) at 60 frames per second.

Pierre Jean Lapray - One of the best experts on this subject based on the ideXlab platform.

  • A 1.3 megapixel FPGA-based smart camera for high dynamic range real time video A 1.3 megapixel FPGA-based smart camera for high dynamic range real time video
    2020
    Co-Authors: Pierre Jean Lapray, Barthélémy Heyrman, Dominique Ginhac, Matthieu Rosse
    Abstract:

    Abstract-A camera is able to capture only a part of a high dynamic range scene information. The same scene can be fully perceived by the human visual system. This is true especially for real scenes where the difference in light intensity between the dark areas and bright areas is high. The imaging technique which can overcome this problem is called HDR (High Dynamic Range). It produces images from a set of multiple LDR images (Low Dynamic Range), captured with different exposure times. This technique appears as one of the most appropriate and a cheap solution to enhance the dynamic range of captured environments. We developed an FPGA-based smart camera that produces a HDR live video colour stream from three successive acquisitions. Our hardware platform is build around a standard LDR CMOS sensor and a Virtex 6 FPGA board. The hardware architecture embeds a multiple exposure control, a memory management unit, the HDR creating, and the tone mapping. Our video camera enables a real-time video at 60 frames per second for a full sensor resolution of 1, 280 × 1, 024 pixels

  • hdr artist an adaptive real time smart camera for high dynamic range imaging
    Journal of Real-time Image Processing, 2016
    Co-Authors: Pierre Jean Lapray, Barthélémy Heyrman, Dominique Ginhac
    Abstract:

    This paper describes a complete FPGA-based smart camera architecture named HDR-ARtiSt (High Dynamic Range Adaptive Real-time Smart camera) which produces a real-time high dynamic range (HDR) live video stream from multiple captures. A specific memory management unit has been defined to adjust the number of acquisitions to improve HDR quality. This smart camera is built around a standard B&W CMOS image sensor and a Xilinx FPGA. It embeds multiple captures, HDR processing, data display and transfer, which is an original contribution compared to the state-of-the-art. The proposed architecture enables a real-time HDR video flow for a full sensor resolution (1.3 Mega pixels) at 60 frames per second.

Barthélémy Heyrman - One of the best experts on this subject based on the ideXlab platform.

  • A 1.3 megapixel FPGA-based smart camera for high dynamic range real time video A 1.3 megapixel FPGA-based smart camera for high dynamic range real time video
    2020
    Co-Authors: Pierre Jean Lapray, Barthélémy Heyrman, Dominique Ginhac, Matthieu Rosse
    Abstract:

    Abstract-A camera is able to capture only a part of a high dynamic range scene information. The same scene can be fully perceived by the human visual system. This is true especially for real scenes where the difference in light intensity between the dark areas and bright areas is high. The imaging technique which can overcome this problem is called HDR (High Dynamic Range). It produces images from a set of multiple LDR images (Low Dynamic Range), captured with different exposure times. This technique appears as one of the most appropriate and a cheap solution to enhance the dynamic range of captured environments. We developed an FPGA-based smart camera that produces a HDR live video colour stream from three successive acquisitions. Our hardware platform is build around a standard LDR CMOS sensor and a Virtex 6 FPGA board. The hardware architecture embeds a multiple exposure control, a memory management unit, the HDR creating, and the tone mapping. Our video camera enables a real-time video at 60 frames per second for a full sensor resolution of 1, 280 × 1, 024 pixels

  • hdr artist an adaptive real time smart camera for high dynamic range imaging
    Journal of Real-time Image Processing, 2016
    Co-Authors: Pierre Jean Lapray, Barthélémy Heyrman, Dominique Ginhac
    Abstract:

    This paper describes a complete FPGA-based smart camera architecture named HDR-ARtiSt (High Dynamic Range Adaptive Real-time Smart camera) which produces a real-time high dynamic range (HDR) live video stream from multiple captures. A specific memory management unit has been defined to adjust the number of acquisitions to improve HDR quality. This smart camera is built around a standard B&W CMOS image sensor and a Xilinx FPGA. It embeds multiple captures, HDR processing, data display and transfer, which is an original contribution compared to the state-of-the-art. The proposed architecture enables a real-time HDR video flow for a full sensor resolution (1.3 Mega pixels) at 60 frames per second.

Neil Audsley - One of the best experts on this subject based on the ideXlab platform.

  • studying the applicability of the scratchpad memory management unit
    Real Time Technology and Applications Symposium, 2010
    Co-Authors: Jack Whitham, Neil Audsley
    Abstract:

    A combination of a scratchpad and scratchpad memory management unit (SMMU) has been proposed as a way to implement fast and time-predictable memory access operations in programs that use dynamic data structures.A memory access operation is time-predictable if its execution time is known or bounded -- this is important within a hard real-time task so that the worst-case execution time (WCET) can be determined. However, the requirement for time-predictability does not remove the conventional requirement for efficiency:operations must be serviced as quickly as possible under worst-case conditions.This paper studies the capabilities of the SMMU when applied to a number of benchmark programs. A new allocation algorithm is proposed to dynamically manage the scratchpad space. In many cases,the SMMU vastly reduces the number of accesses to dynamic data structures stored in external memory along the worst-case execution path (WCEP). Across all the benchmarks,an average of 47% of accesses are rerouted to scratchpad, with nearly100% for some programs. In previous scratchpad-based work, time-predictability could only be assured for these operations using external memory.The paper also examines situations in which the SMMU does not perform so well, and discusses how these could be addressed.

  • predictable and efficient virtual addressing for safety critical real time systems
    Euromicro Conference on Real-Time Systems, 2001
    Co-Authors: M D Bennett, Neil Audsley
    Abstract:

    Conventionally, the use of virtual memory in safety-critical real-time systems has been avoided, one reason being the difficulties it provides to timing analysis. The difficulties arise due to the memory management unit (MMU) on commercial processors being optimised to improve average performance, to the detriment of simple worst-case analysis. However within safety-critical systems, there is a move towards implementations where processes of differing integrity levels are allocated to the same processor. This requires adequate partitioning between processes of different integrity levels. One method for achieving this in the context of commercial processor is via use of the MMU and its support for virtual memory. The focus of this paper is upon the provision of virtual memory for processes of all integrity levels without complicating the timing analysis of safety-critical processes with hard deadlines. Also, for lower integrity processes without hard deadlines, the flexibility of the virtual memory provided does not restrict the process functionality, The virtual memory system proposed is generic and can be implemented on many commercial architectures e.g. PowerPC, ARM and MIPS. This paper details the PowerPC implementation.

Paulo Licio De Geus - One of the best experts on this subject based on the ideXlab platform.

  • Arquitetura de um microcomputador para controle de processos concorrentes em tempo real
    2014
    Co-Authors: Paulo Licio De Geus
    Abstract:

    Resumo: Este trabalho descreve. Modificações introduzidas sobre a arquitetura existente de um microcomputador modular para atender requisitos de novas aplicações propostas. Tais aplicações envolvem aquisição de dados e processamento em tempo rea1 , além do gerenciamento de um grande número de interfaces de comunicação série. O objetivo procurado foi a obtenção de um sistema com baixo tempo de resposta a eventos assíncronos, otimização do fluxo de dados e boa taxa de processamento, dentro das limitações de gerenciamento de memória implícitas à CPU"de 8 bits utilizada. As principais modificações de hardware introduzidas são: uma unidade de gerenciamento de memória. com página.s de 4 Kbytes é 64 contextos de paginação residentes; um esquema de interrupções vetorizadas (família Z80) para a identificação automática de até 128 eventos diferentes; um controlador de DMA dispondo de 11 canais independentes com acesso ao espaço total de 1 Mbyte do microcomputadorAbstract: This work describes enhancements made over the existing architecture of a modular microcomputer to support the requirements of proposed new applications. Such applications involve data aquisition and real-time processing, as well as the management of several serial communication interfaces. The desired goal was to get a system with low response time to asynchronous events, optimized data flow and good throughput, within the memory management limitations implied by the use of an 8 bit CPU. The main hardware alterations are: a memory-management unit with 4K byte pages and 54 resident pagination contexts; a vectorized interrupt scheme (Z80 family) for automatic identification of up to 128 different events; a DMA controller supporting 11 independent channels, with access to the full 1 Mbyte space of the microcompute