The Experts below are selected from a list of 174951 Experts worldwide ranked by ideXlab platform
David Blaauw - One of the best experts on this subject based on the ideXlab platform.
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statistical Timing Analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003Co-Authors: Aseem Agarwal, Vladimir Zolotov, David BlaauwAbstract:The growing impact of within-die process variation has created the need for statistical Timing Analysis, where gate delays are modeled as random variables. Statistical Timing Analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical Timing Analysis which uses statistical bounds and selective enumeration to refine these bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical Timing Analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. If the computed bounds are not sufficiently close to each other, we propose a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error, which can be further reduced using selective enumeration with modest additional run time.
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Slope propagation in static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002Co-Authors: David Blaauw, Vasily Zolotov, Savithri SundareswaranAbstract:Static Timing Analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional Timing Analysis approach can report an optimistic circuit delay and may identify the wrong critical path. Also, the calculated circuit delay is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. The authors also examine an alternate approach where the propagated signal is constructed by combining the latest arrival time and the slowest transition time from all signals incident on a node. While this approach remedies the problem of discontinuity, it can significantly overestimate the circuit delay and can also identify the wrong critical path. In this paper, they therefore propose a new Timing Analysis algorithm and prove that it computes the correct and continuous Timing graph delay and the proper critical path. The proposed algorithm selectively propagates multiple signals through each Timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. They show that the algorithm propagates the sufficient and necessary set of signals for computing the delay of a general Timing graph. The authors also introduce a new property of digital gates, referred to as the transition shift property, and, using this property, show that the number of propagated signals can be significantly reduced for Timing graphs of digital circuits. Finally, they discuss the computation of required times and node slacks for the traditional approaches and propose corresponding algorithms for the new approaches. They show that while the traditional approach can incur both a positive or negative error in the computed slack, the proposed algorithms compute a conservative slack for off-critical nodes and the correct and continuous slack for the critical path. The proposed algorithms were implemented in an industrial static Timing Analysis and optimization tool, and the authors present results for a number of industrial circuits. Their results show that the traditional Timing Analysis method underestimates the circuit delay by as much as 39%, while the discussed alternate approach can overestimate circuit delay by as much as 17%. The proposed method computes the correct delay, while incurring only a small run time overhead in all cases.
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DATE - Statistical Timing Analysis Using Bounds
2003 Design Automation and Test in Europe Conference and Exhibition, 1Co-Authors: Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma VrudhulaAbstract:The growing impact of within-die process variation has created the need for statistical Timing Analysis, where gate delays are modeled as random variables. Statistical Timing Analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper we propose a new approach to statistical Timing Analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical Timing Analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.
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ICCAD - Slope propagation in static Timing Analysis
IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1Co-Authors: David Blaauw, Savithri Sundareswaran, Vladimir Zolotov, Rajendran PandaAbstract:Static Timing Analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for Timing Analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new Timing Analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each Timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional Timing Analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static Timing Analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional Timing Analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.
Rajendran Panda - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - Slope propagation in static Timing Analysis
IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1Co-Authors: David Blaauw, Savithri Sundareswaran, Vladimir Zolotov, Rajendran PandaAbstract:Static Timing Analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for Timing Analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new Timing Analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each Timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional Timing Analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static Timing Analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional Timing Analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.
Vladimir Zolotov - One of the best experts on this subject based on the ideXlab platform.
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statistical Timing Analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003Co-Authors: Aseem Agarwal, Vladimir Zolotov, David BlaauwAbstract:The growing impact of within-die process variation has created the need for statistical Timing Analysis, where gate delays are modeled as random variables. Statistical Timing Analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical Timing Analysis which uses statistical bounds and selective enumeration to refine these bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical Timing Analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. If the computed bounds are not sufficiently close to each other, we propose a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error, which can be further reduced using selective enumeration with modest additional run time.
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DATE - Statistical Timing Analysis Using Bounds
2003 Design Automation and Test in Europe Conference and Exhibition, 1Co-Authors: Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma VrudhulaAbstract:The growing impact of within-die process variation has created the need for statistical Timing Analysis, where gate delays are modeled as random variables. Statistical Timing Analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper we propose a new approach to statistical Timing Analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical Timing Analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.
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ICCAD - Slope propagation in static Timing Analysis
IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1Co-Authors: David Blaauw, Savithri Sundareswaran, Vladimir Zolotov, Rajendran PandaAbstract:Static Timing Analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for Timing Analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new Timing Analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each Timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional Timing Analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static Timing Analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional Timing Analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.
Ahmed Shebaita - One of the best experts on this subject based on the ideXlab platform.
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tau 2013 variation aware Timing Analysis contest
International Symposium on Physical Design, 2013Co-Authors: Debjit Sinha, Luis Guerra E Silva, Jia Wang, Shesha Raghunathan, Dileep N Netrabile, Ahmed ShebaitaAbstract:Timing Analysis is a key component of any integrated circuit (IC) chip design-closure flow, and is employed at various stages of the flow including pre/post-route Timing optimization and Timing signoff. While accurate Timing Analysis is important, the run-time of the Analysis is equally critical with growing chip design sizes and complexity (for example, increasing number of clocks domains, voltage islands, etc.). In addition, the increasing significance of variability in the chip manufacturing process as well as environmental variability necessitates use of variation aware techniques (e.g. statistical, multi-corner) for chip Timing Analysis which significantly impacts the Analysis run-time. The aim of the TAU 2013 variation aware Timing contest is to seek novel ideas for fast variation aware Timing Analysis, by means of the following: (a) increase awareness of variation aware Timing Analysis and provide insight into some challenging aspects of the Analysis, (b) encourage novel parallelization techniques (including multi-threading) for Timing Analysis, and (c) facilitate creation of a publicly available variation aware Timing Analysis framework and benchmarks to further advance research in this area.
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ISPD - TAU 2013 variation aware Timing Analysis contest
Proceedings of the 2013 ACM international symposium on International symposium on physical design - ISPD '13, 2013Co-Authors: Debjit Sinha, Jia Wang, Shesha Raghunathan, Dileep N Netrabile, Luis Guerra E Silva, Ahmed ShebaitaAbstract:Timing Analysis is a key component of any integrated circuit (IC) chip design-closure flow, and is employed at various stages of the flow including pre/post-route Timing optimization and Timing signoff. While accurate Timing Analysis is important, the run-time of the Analysis is equally critical with growing chip design sizes and complexity (for example, increasing number of clocks domains, voltage islands, etc.). In addition, the increasing significance of variability in the chip manufacturing process as well as environmental variability necessitates use of variation aware techniques (e.g. statistical, multi-corner) for chip Timing Analysis which significantly impacts the Analysis run-time. The aim of the TAU 2013 variation aware Timing contest is to seek novel ideas for fast variation aware Timing Analysis, by means of the following: (a) increase awareness of variation aware Timing Analysis and provide insight into some challenging aspects of the Analysis, (b) encourage novel parallelization techniques (including multi-threading) for Timing Analysis, and (c) facilitate creation of a publicly available variation aware Timing Analysis framework and benchmarks to further advance research in this area.
Savithri Sundareswaran - One of the best experts on this subject based on the ideXlab platform.
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Slope propagation in static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002Co-Authors: David Blaauw, Vasily Zolotov, Savithri SundareswaranAbstract:Static Timing Analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional Timing Analysis approach can report an optimistic circuit delay and may identify the wrong critical path. Also, the calculated circuit delay is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. The authors also examine an alternate approach where the propagated signal is constructed by combining the latest arrival time and the slowest transition time from all signals incident on a node. While this approach remedies the problem of discontinuity, it can significantly overestimate the circuit delay and can also identify the wrong critical path. In this paper, they therefore propose a new Timing Analysis algorithm and prove that it computes the correct and continuous Timing graph delay and the proper critical path. The proposed algorithm selectively propagates multiple signals through each Timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. They show that the algorithm propagates the sufficient and necessary set of signals for computing the delay of a general Timing graph. The authors also introduce a new property of digital gates, referred to as the transition shift property, and, using this property, show that the number of propagated signals can be significantly reduced for Timing graphs of digital circuits. Finally, they discuss the computation of required times and node slacks for the traditional approaches and propose corresponding algorithms for the new approaches. They show that while the traditional approach can incur both a positive or negative error in the computed slack, the proposed algorithms compute a conservative slack for off-critical nodes and the correct and continuous slack for the critical path. The proposed algorithms were implemented in an industrial static Timing Analysis and optimization tool, and the authors present results for a number of industrial circuits. Their results show that the traditional Timing Analysis method underestimates the circuit delay by as much as 39%, while the discussed alternate approach can overestimate circuit delay by as much as 17%. The proposed method computes the correct delay, while incurring only a small run time overhead in all cases.
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ICCAD - Slope propagation in static Timing Analysis
IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1Co-Authors: David Blaauw, Savithri Sundareswaran, Vladimir Zolotov, Rajendran PandaAbstract:Static Timing Analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for Timing Analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new Timing Analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each Timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional Timing Analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static Timing Analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional Timing Analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.
