The Experts below are selected from a list of 261 Experts worldwide ranked by ideXlab platform
Kiran Kumar Abburi - One of the best experts on this subject based on the ideXlab platform.
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VLSI Design - A Scalable LDPC Decoder on GPU
2011 24th Internatioal Conference on VLSI Design, 2011Co-Authors: Kiran Kumar AbburiAbstract:A flexible and scalable approach for LDPC decodingon CUDA based Graphics Processing Unit (GPU) is presented in this paper. Layered decoding is a popular method for LDPC decoding and is known for its fast convergence. However, efficient implementation of the layered decoding algorithm on GPU is challenging due to the limited amount of data-parallelism available in this algorithm. To overcome this problem, a kernel execution configuration that can decode multiple codewords simultaneously on GPU is developed. This paper proposes a compact data packing scheme to reduce the number of global Memory accesses and parity-check matrix representation to reduce constant Memory latency. Global Memory bandwidth efficiency is improved by coalescing simultaneous Memory accesses of threads in a half-warp into a single Memory Transaction. Asynchronous data transfers are used to hide host Memory latency by overlapping kernel execution with data transfers between CPU and GPU. The proposed implementation of LDPC decoder on GPU performs two orders of magnitude faster than the LDPC decoder on a CPU and four times faster than the previously reported LDPC decoder on GPU. This implementation achieves a throughput of 160Mbps, which is comparable to dedicated hardware solutions.
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A Scalable LDPC Decoder on GPU
2011 24th Internatioal Conference on VLSI Design, 2011Co-Authors: Kiran Kumar AbburiAbstract:A flexible and scalable approach for LDPC decoding on CUDA based Graphics Processing Unit (GPU) is presented in this paper. Layered decoding is a popular method for LDPC decoding and is known for its fast convergence. However, efficient implementation of the layered decoding algorithm on GPU is challenging due to the limited amount of data-parallelism available in this algorithm. To overcome this problem, a kernel execution configuration that can decode multiple codewords simultaneously on GPU is developed. This paper proposes a compact data packing scheme to reduce the number of global Memory accesses and parity-check matrix representation to reduce constant Memory latency. Global Memory bandwidth efficiency is improved by coalescing simultaneous Memory accesses of threads in a half-warp into a single Memory Transaction. Asynchronous data transfers are used to hide host Memory latency by overlapping kernel execution with data transfers between CPU and GPU. The proposed implementation of LDPC decoder on GPU performs two orders of magnitude faster than the LDPC decoder on a CPU and four times faster than the previously reported LDPC decoder on GPU. This implementation achieves a throughput of 160Mbps, which is comparable to dedicated hardware solutions.
Yingjun Wu - One of the best experts on this subject based on the ideXlab platform.
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scalable in Memory Transaction processing with htm
USENIX Annual Technical Conference, 2016Co-Authors: Yingjun WuAbstract:We propose a new HTM-assisted concurrency control protocol, called HTCC, that achieves high scalability and robustness when processing OLTP workloads. HTCC attains its goal using a two-pronged strategy that exploits the strengths of HTM. First, it distinguishes between hot and cold records, and deals with each type differently - while accesses to highly contended data are protected using conventional fine-grained locks, accesses to cold data are HTM-guarded. This remarkably reduces the database Transaction abort rate and exploits HTM's effectiveness in executing low-contention critical sections. Second, to minimize the overhead inherited from successive restarts of aborted database Transactions, HTCC caches the internal execution states of a Transaction for performing delta-restoration, which partially updates the maintained read/write set and bypasses redundant index lookups during Transaction re-execution at best effort. This approach is greatly facilitated by HTM's speedy hardware mechanism for ensuring atomicity and isolation. We evaluated HTCC in a main-Memory database prototype running on a 4 socket machine (40 cores in total), and confirmed that HTCC can scale near-linearly, yielding high Transaction rate even under highly contended workloads.
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USENIX Annual Technical Conference - Scalable in-Memory Transaction processing with HTM
2016Co-Authors: Yingjun WuAbstract:We propose a new HTM-assisted concurrency control protocol, called HTCC, that achieves high scalability and robustness when processing OLTP workloads. HTCC attains its goal using a two-pronged strategy that exploits the strengths of HTM. First, it distinguishes between hot and cold records, and deals with each type differently - while accesses to highly contended data are protected using conventional fine-grained locks, accesses to cold data are HTM-guarded. This remarkably reduces the database Transaction abort rate and exploits HTM's effectiveness in executing low-contention critical sections. Second, to minimize the overhead inherited from successive restarts of aborted database Transactions, HTCC caches the internal execution states of a Transaction for performing delta-restoration, which partially updates the maintained read/write set and bypasses redundant index lookups during Transaction re-execution at best effort. This approach is greatly facilitated by HTM's speedy hardware mechanism for ensuring atomicity and isolation. We evaluated HTCC in a main-Memory database prototype running on a 4 socket machine (40 cores in total), and confirmed that HTCC can scale near-linearly, yielding high Transaction rate even under highly contended workloads.
Adrian Cristal - One of the best experts on this subject based on the ideXlab platform.
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PACT - Supporting stateful tasks in a dataflow graph
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: Vladimir Gajinov, Osman S. Ünsal, Tim Harris, Eduard Ayguadé, Srdjan Stipic, Adrian CristalAbstract:This paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-Memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language constructs that allow a programmer to delineate a program into a set of tasks and to explicitly define input data for each task. This information is conveyed to the ADF runtime system which constructs the task dependency graph and builds the necessary infrastructure for dataflow execution. However, the key aspect of the proposed model is that it does not require the programmer to specify all of the task's dependencies explicitly, but only those that imply logical ordering between tasks. The ADF model manages the remainder of inter-task dependencies automatically, by executing the body of the task within an implicit Memory Transaction. This provides an easy-to-program optimistic concurrency substrate and enables a task to safely share data with other concurrent tasks. In this paper, we describe the ADF model and show how it can increase the programmability of shared Memory systems.
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Supporting stateful tasks in a dataflow graph
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: Vladimir Gajinov, Srdjan Stipić, Osman S. Ünsal, Tim Harris, Eduard Ayguadé, Adrian CristalAbstract:This paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-Memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language constructs that allow a programmer to delineate a program into a set of tasks and to explicitly define input data for each task. This information is conveyed to the ADF runtime system which constructs the task dependency graph and builds the necessary infrastructure for dataflow execution. However, the key aspect of the proposed model is that it does not require the programmer to specify all of the task's dependencies explicitly, but only those that imply logical ordering between tasks. The ADF model manages the remainder of inter-task dependencies automatically, by executing the body of the task within an implicit Memory Transaction. This provides an easy-to-program optimistic concurrency substrate and enables a task to safely share data with other concurrent tasks. In this paper, we describe the ADF model and show how it can increase the programmability of shared Memory systems. Copyright © 2012 by the Association for Computing Machinery, Inc. (ACM).
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Supporting stateful tasks in a dataflow graph
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012Co-Authors: Vladimir Gajinov, Osman S. Ünsal, Tim Harris, Eduard Ayguadé, Srdjan Stipic, Adrian CristalAbstract:This paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-Memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language constructs that allow a programmer to delineate a program into a set of tasks and to explicitly define input data for each task. This information is conveyed to the ADF runtime system which constructs the task dependency graph and builds the necessary infrastructure for dataflow execution. However, the key aspect of the proposed model is that it does not require the programmer to specify all of the task's dependencies explicitly, but only those that imply logical ordering between tasks. The ADF model manages the remainder of inter-task dependencies automatically, by executing the body of the task within an implicit Memory Transaction. This provides an easy-to-program optimistic concurrency substrate and enables a task to safely share data with other concurrent tasks. In this paper, we describe the ADF model and show how it can increase the programmability of shared Memory systems.
Gerhard Fettweis - One of the best experts on this subject based on the ideXlab platform.
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Statistical Access Interval Prediction for Tightly Coupled Memory Systems
2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2019Co-Authors: Robert Wittig, Mattis Hasler, Emil Matus, Gerhard FettweisAbstract:Sharing Memory in embedded systems presents a promising approach to increase the area utilization of these constraint platforms. However, sharing inevitably results in access conflicts, which diminish the overall system performance. As a counter measure, we propose Access Interval Prediction. We argue that most Memory Transaction of embedded processors can be reliably predicted in the time domain. Therefore, preallocation of shared resources can be used to avoid collisions in the Memory system. Our statistical model shows an accuracy of over 90 percent, thus significantly reducing Memory contention.
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COOL CHIPS - Statistical Access Interval Prediction for Tightly Coupled Memory Systems
2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2019Co-Authors: Robert Wittig, Mattis Hasler, Emil Matus, Gerhard FettweisAbstract:Sharing Memory in embedded systems presents a promising approach to increase the area utilization of these constraint platforms. However, sharing inevitably results in access conflicts, which diminish the overall system performance. As a counter measure, we propose Access Interval Prediction. We argue that most Memory Transaction of embedded processors can be reliably predicted in the time domain. Therefore, preallocation of shared resources can be used to avoid collisions in the Memory system. Our statistical model shows an accuracy of over 90 percent, thus significantly reducing Memory contention.
Yvon Savaria - One of the best experts on this subject based on the ideXlab platform.
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A Memory Transaction model for Sparse Matrix-Vector multiplications on GPUs
2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014Co-Authors: Thalie Keklikian, J. Pierre M. Langlois, Yvon SavariaAbstract:The Sparse Matrix-Vector multiplication (SpMV) is an algorithm used in many fields. Since the introduction of CUDA and general purpose programming on GPUs, several efforts to optimize it have been reported. SpMV optimization is complex due to irregular Memory accesses depending on the nonzero element distribution of the matrix. In this paper, we propose a model that predicts the number of Memory Transactions of SpMV for a matrix stored in the CSR format. With the number of Memory Transactions known in advance, the performance and the execution time can be estimated. The model can be used to select the best suited CUDA implementation for sparse matrices for a given application domain. Predicted results from the model are within 7.5% for the matrices of more than 1000 rows that we have tested on the NVIDIA Tesla K20c and Ge-Force GTX 670.
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NEWCAS - A Memory Transaction model for Sparse Matrix-Vector multiplications on GPUs
2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014Co-Authors: Thalie Keklikian, J. M. Pierre Langlois, Yvon SavariaAbstract:The Sparse Matrix-Vector multiplication (SpMV) is an algorithm used in many fields. Since the introduction of CUDA and general purpose programming on GPUs, several efforts to optimize it have been reported. SpMV optimization is complex due to irregular Memory accesses depending on the nonzero element distribution of the matrix. In this paper, we propose a model that predicts the number of Memory Transactions of SpMV for a matrix stored in the CSR format. With the number of Memory Transactions known in advance, the performance and the execution time can be estimated. The model can be used to select the best suited CUDA implementation for sparse matrices for a given application domain. Predicted results from the model are within 7.5% for the matrices of more than 1000 rows that we have tested on the NVIDIA Tesla K20c and Ge-Force GTX 670.