The Experts below are selected from a list of 21513 Experts worldwide ranked by ideXlab platform

Satoshi Sugahara - One of the best experts on this subject based on the ideXlab platform.

  • nonvolatile static random access memory using resistive switching devices variable transconductance metal oxide semiconductor field effect Transistor approach
    Japanese Journal of Applied Physics, 2010
    Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
    Abstract:

    In this paper, we present a variable-transconductance (gm) metal–oxide–semiconductor Field-Effect-Transistor (VGm-MOSFET) architecture using a nonpolar resistive switching device (RSD) for nonvolatile bistable circuit applications. The architecture can be achieved by connecting an RSD to the source terminal of an ordinary MOSFET. The current drive capability of the VGm-MOSFET can be modified by resistance states of the connected RSD, which is a very useful function for nonvolatile bistable circuits, such as nonvolatile static random access memory (NV-SRAM) and nonvolatile flip-flop (NV-FF). NV-SRAM can be easily configured by connecting two additional VGm-MOSFETs to the storage nodes of a standard SRAM cell. Using our developed SPICE macromodel for nonpolar RSDs, successful circuit operations of the proposed NV-SRAM cell were confirmed.

  • a new spin functional metal oxide semiconductor field effect Transistor based on magnetic tunnel junction technology pseudo spin mosfet
    Applied Physics Express, 2010
    Co-Authors: Yusuke Shuto, Masaaki Tanaka, Shuuichirou Yamamoto, Ryosho Nakane, Wenhong Wang, Hiroaki Sukegawa, Koichiro Inomata, Satoshi Sugahara
    Abstract:

    We fabricated and characterized a new spin-functional metal–oxide–semiconductor Field-Effect Transistor (MOSFET) referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit using an ordinary MOSFET and magnetic tunnel junction (MTJ) for reproducing functions of spin-Transistors. Device integration techniques for a bottom gate MOSFET using a silicon-on-insulator (SOI) substrate and for an MTJ with a full-Heusler alloy electrode and MgO tunnel barrier were developed. The fabricated PS-MOSFET exhibited high and low transconductance controlled by the magnetization configurations of the MTJ at room temperature. This is the first observation of spin-Transistor operations for spin-functional MOSFETs.

  • nonvolatile static random access memory based on spin Transistor architecture
    Journal of Applied Physics, 2009
    Co-Authors: Yusuke Shuto, Shuuichirou Yamamoto, Satoshi Sugahara
    Abstract:

    The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin Transistor comprised of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin Transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

  • Nonvolatile static random access memory based on spin-Transistor architecture
    Journal of Applied Physics, 2009
    Co-Authors: Satoshi Sugahara
    Abstract:

    The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin Transistor comprised of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin Transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin Transistor comprised of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin Transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

  • a spin metal oxide semiconductor field effect Transistor using half metallic ferromagnet contacts for the source and drain
    Applied Physics Letters, 2004
    Co-Authors: Satoshi Sugahara, Masaaki Tanaka
    Abstract:

    We propose and theoretically analyze a metal–oxide–semiconductor Field-Effect-Transistor (MOSFET) type of spin Transistor (spin MOSFET) consisting of a MOS structure and half-metallic-ferromagnet (HMF) contacts for the source and drain. When the magnetization configuration of the HMF source and drain is parallel (antiparallel), highly spin-polarized carriers injected from the HMF source to the channel are transported into (blocked by) the HMF drain, resulting in the magnetization-configuration-dependent output characteristics. Our two-dimensional numerical analysis indicates that the spin MOSFET exhibits high (low) current drive capability in the parallel (antiparallel) magnetization, and that extremely large magnetocurrent ratios can be obtained. Furthermore, the spin MOSFET satisfies other important requirements for “spintronic integrated circuits,” such as high amplification capability, low power-delay product, and low off-current.

Masaaki Tanaka - One of the best experts on this subject based on the ideXlab platform.

  • large current modulation and tunneling magnetoresistance change by a side gate electric field in a gamnas based vertical spin metal oxide semiconductor field effect Transistor
    Scientific Reports, 2018
    Co-Authors: Toshiki Kanaki, Shinobu Ohya, Hiroki Yamasaki, Tomohiro Koyama, Daichi Chiba, Masaaki Tanaka
    Abstract:

    A vertical spin Metal-Oxide-Semiconductor Field-Effect Transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current IDS modulation by a gate-source voltage VGS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin Field-Effect Transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large IDS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that IDS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by VGS. This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

  • spin dependent transport properties of a gamnas based vertical spin metal oxide semiconductor field effect Transistor structure
    Applied Physics Letters, 2015
    Co-Authors: Toshiki Kanaki, Hirokatsu Asahara, Shinobu Ohya, Masaaki Tanaka
    Abstract:

    We fabricate a vertical spin Metal-Oxide-Semiconductor Field-Effect Transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current IDS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate IDS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

  • a new spin functional metal oxide semiconductor field effect Transistor based on magnetic tunnel junction technology pseudo spin mosfet
    Applied Physics Express, 2010
    Co-Authors: Yusuke Shuto, Masaaki Tanaka, Shuuichirou Yamamoto, Ryosho Nakane, Wenhong Wang, Hiroaki Sukegawa, Koichiro Inomata, Satoshi Sugahara
    Abstract:

    We fabricated and characterized a new spin-functional metal–oxide–semiconductor Field-Effect Transistor (MOSFET) referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit using an ordinary MOSFET and magnetic tunnel junction (MTJ) for reproducing functions of spin-Transistors. Device integration techniques for a bottom gate MOSFET using a silicon-on-insulator (SOI) substrate and for an MTJ with a full-Heusler alloy electrode and MgO tunnel barrier were developed. The fabricated PS-MOSFET exhibited high and low transconductance controlled by the magnetization configurations of the MTJ at room temperature. This is the first observation of spin-Transistor operations for spin-functional MOSFETs.

  • a spin metal oxide semiconductor field effect Transistor using half metallic ferromagnet contacts for the source and drain
    Applied Physics Letters, 2004
    Co-Authors: Satoshi Sugahara, Masaaki Tanaka
    Abstract:

    We propose and theoretically analyze a metal–oxide–semiconductor Field-Effect-Transistor (MOSFET) type of spin Transistor (spin MOSFET) consisting of a MOS structure and half-metallic-ferromagnet (HMF) contacts for the source and drain. When the magnetization configuration of the HMF source and drain is parallel (antiparallel), highly spin-polarized carriers injected from the HMF source to the channel are transported into (blocked by) the HMF drain, resulting in the magnetization-configuration-dependent output characteristics. Our two-dimensional numerical analysis indicates that the spin MOSFET exhibits high (low) current drive capability in the parallel (antiparallel) magnetization, and that extremely large magnetocurrent ratios can be obtained. Furthermore, the spin MOSFET satisfies other important requirements for “spintronic integrated circuits,” such as high amplification capability, low power-delay product, and low off-current.

  • a spin metal oxide semiconductor field effect Transistor using half metallic ferromagnet contacts for the source and drain
    arXiv: Materials Science, 2003
    Co-Authors: Satoshi Sugahara, Masaaki Tanaka
    Abstract:

    We propose and theoretically analyze a novel Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) type of spin Transistor (hereafter referred to as a spin MOSFET) consisting of a MOS gate structure and half-metallic-ferromagnet (HMF) contacts for the source and drain. When the magnetization configuration between the HMF source and drain is parallel (antiparallel), highly spin-polarized carriers injected from the HMF source to the channel are transported into (blocked by) the HMF drain, resulting in the magnetization-configuration-dependent output characteristics. Our two-dimensional numerical analysis indicates that the spin MOSFET exhibits high (low) current drive capability in the parallel (antiparallel) magnetization, and that extremely large magnetocurrent ratios can be obtained. Furthermore, the spin MOSFET satisfies other important requirements for "spintronic" integrated circuits, such as high amplification capability, low power-delay product, and low off-current.

Toshiki Kanaki - One of the best experts on this subject based on the ideXlab platform.

  • large current modulation and tunneling magnetoresistance change by a side gate electric field in a gamnas based vertical spin metal oxide semiconductor field effect Transistor
    Scientific Reports, 2018
    Co-Authors: Toshiki Kanaki, Shinobu Ohya, Hiroki Yamasaki, Tomohiro Koyama, Daichi Chiba, Masaaki Tanaka
    Abstract:

    A vertical spin Metal-Oxide-Semiconductor Field-Effect Transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current IDS modulation by a gate-source voltage VGS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin Field-Effect Transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large IDS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that IDS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by VGS. This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

  • spin dependent transport properties of a gamnas based vertical spin metal oxide semiconductor field effect Transistor structure
    Applied Physics Letters, 2015
    Co-Authors: Toshiki Kanaki, Hirokatsu Asahara, Shinobu Ohya, Masaaki Tanaka
    Abstract:

    We fabricate a vertical spin Metal-Oxide-Semiconductor Field-Effect Transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current IDS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate IDS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

Yusuke Shuto - One of the best experts on this subject based on the ideXlab platform.

  • nonvolatile static random access memory using resistive switching devices variable transconductance metal oxide semiconductor field effect Transistor approach
    Japanese Journal of Applied Physics, 2010
    Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
    Abstract:

    In this paper, we present a variable-transconductance (gm) metal–oxide–semiconductor Field-Effect-Transistor (VGm-MOSFET) architecture using a nonpolar resistive switching device (RSD) for nonvolatile bistable circuit applications. The architecture can be achieved by connecting an RSD to the source terminal of an ordinary MOSFET. The current drive capability of the VGm-MOSFET can be modified by resistance states of the connected RSD, which is a very useful function for nonvolatile bistable circuits, such as nonvolatile static random access memory (NV-SRAM) and nonvolatile flip-flop (NV-FF). NV-SRAM can be easily configured by connecting two additional VGm-MOSFETs to the storage nodes of a standard SRAM cell. Using our developed SPICE macromodel for nonpolar RSDs, successful circuit operations of the proposed NV-SRAM cell were confirmed.

  • a new spin functional metal oxide semiconductor field effect Transistor based on magnetic tunnel junction technology pseudo spin mosfet
    Applied Physics Express, 2010
    Co-Authors: Yusuke Shuto, Masaaki Tanaka, Shuuichirou Yamamoto, Ryosho Nakane, Wenhong Wang, Hiroaki Sukegawa, Koichiro Inomata, Satoshi Sugahara
    Abstract:

    We fabricated and characterized a new spin-functional metal–oxide–semiconductor Field-Effect Transistor (MOSFET) referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit using an ordinary MOSFET and magnetic tunnel junction (MTJ) for reproducing functions of spin-Transistors. Device integration techniques for a bottom gate MOSFET using a silicon-on-insulator (SOI) substrate and for an MTJ with a full-Heusler alloy electrode and MgO tunnel barrier were developed. The fabricated PS-MOSFET exhibited high and low transconductance controlled by the magnetization configurations of the MTJ at room temperature. This is the first observation of spin-Transistor operations for spin-functional MOSFETs.

  • nonvolatile static random access memory based on spin Transistor architecture
    Journal of Applied Physics, 2009
    Co-Authors: Yusuke Shuto, Shuuichirou Yamamoto, Satoshi Sugahara
    Abstract:

    The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin Transistor comprised of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin Transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

Shinobu Ohya - One of the best experts on this subject based on the ideXlab platform.

  • large current modulation and tunneling magnetoresistance change by a side gate electric field in a gamnas based vertical spin metal oxide semiconductor field effect Transistor
    Scientific Reports, 2018
    Co-Authors: Toshiki Kanaki, Shinobu Ohya, Hiroki Yamasaki, Tomohiro Koyama, Daichi Chiba, Masaaki Tanaka
    Abstract:

    A vertical spin Metal-Oxide-Semiconductor Field-Effect Transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current IDS modulation by a gate-source voltage VGS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin Field-Effect Transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large IDS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that IDS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by VGS. This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

  • spin dependent transport properties of a gamnas based vertical spin metal oxide semiconductor field effect Transistor structure
    Applied Physics Letters, 2015
    Co-Authors: Toshiki Kanaki, Hirokatsu Asahara, Shinobu Ohya, Masaaki Tanaka
    Abstract:

    We fabricate a vertical spin Metal-Oxide-Semiconductor Field-Effect Transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current IDS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate IDS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.