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Arutyunyan Levon Lorisovich - One of the best experts on this subject based on the ideXlab platform.

  • The language means of synthesis of the Microprogram supports
    1992
    Co-Authors: Arutyunyan Levon Lorisovich
    Abstract:

    The object of investigation: the Microprogram level of the Microprogramed processors, Microprogram-realized algorithms. The purpose of the work: the development of language means for adaptation of the Microprogram level and corresponding algorithmic and program support. Developed have been the system of parameters, the algorithms of optimization of the multilevel models parameters values, the algorithms for determination of invariants and information characteristics. The development of the language means for adaptation of comters series EC and the language of synthesis of the design automatic system microcode of plug-in cards for PK represent the practical results. The investigation results have been introduced in the APO "Electron" and in the Kasansky Computer Plant. The subject of introduction: the language means and the program system for the determination of the parameters values of adaptation systems of Computer EC-1046, MBK46, Computer EC-1170, plug-in cards design systems for the PKAvailable from VNTIC / VNTIC - Scientific & Technical Information Centre of RussiaSIGLERURussian Federatio

Amiya Nayak - One of the best experts on this subject based on the ideXlab platform.

  • MICRO - A survey on bit dimension optimization strategies of Microprograms
    [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture, 1
    Co-Authors: Sunil R. Das, Amiya Nayak
    Abstract:

    Microprogram optimization is one way to increase efficiency, and optimization can be crucial in some applications. Optimization refers to a reduction of execution time of Microprograms, or of the control store size, B × W, where W represents the word dimension of the control store which is the number of words of control store required for certain application, and B represents the bit dimension which is the number of bits per word of control store. The various optimization strategies can be broadly classified under four categories : bit dimension reduction, word dimension reduction, state reduction, and heuristic reduction. A survey of the various bit dimension optimization techniques has been presented by Agerwala in his 1976 paper, where the techniques are critically analyzed and compared, and the results of analysis are discussed. This paper further augments the work of Agerwala, taking into account the optimization methods developed later and hence not discussed by him. Also, the present study considers the optimization problem in the case of polyphase microinstructions in addition to that for monophase microinstructions. The prospective, current status, and future trends in this direction are also briefly outlined.

Ward, Michael John - One of the best experts on this subject based on the ideXlab platform.

  • A machine-independent Microprogram development system
    Faculty of Science Computer Science, 2013
    Co-Authors: Ward, Michael John
    Abstract:

    The aims of this project are twofold. They are firstly, to implement a Microprogram development system that allows the programmer to write microcode for any Microprogrammable machine, and secondly, to build a Microprogrammable machine, incorporating the user friendliness of a simulator, while still providing the 'hands on' experience obtained actual hardware. Microprogram development involves a two stage process. The first step is to describe the target machine, using format descriptions and mnemonic-based template definitions. The second stage involves using the defined mnemonics to write the microcodes for the target machine. This includes an assembly phase to translate the mnemonics into the binary microinstructions. Three main components constitute the Microprogrammable machine. The Arithmetic and Logic Unit (ALU) is built using chips from Advanced Micro Devices' Am29ØØ bit-slice family, the action of the Microprogram Control Unit (MCU) is simulated by software running on an IBM Personal Computer, and a section of the IBM PC's main memory acts as the Control Store (CS) for the system. The ALU is built on a prototyping card that plugs into one of the slots on the IBM PC's mother board. A hardware simulator program, that produces the effect of the ALU, has also been developed. A small assembly language has been developed using the system, to test the various functions of the system. A mini-assembler has also been written to facilitate assembly of the above language. A group of honours students at Rhodes University tested the Microprogram development system. Their ideas and suggestions have been tabulated in this report and some of them have been used to enhance the system's performance. The concept of allowing 'inline' microinstructions in the macroprogram is also investigated in this report and a method of implementing this is shown

Larysa Titarenko - One of the best experts on this subject based on the ideXlab platform.

  • REDUCTION IN THE NUMBER OF LUT ELEMENTS FOR CONTROL UNITS WITH CODE SHARING
    2013
    Co-Authors: Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Abstract:

    Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional Microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a Microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given

  • EWDTS - Compositional Microprogram control unit with operational automaton of transitions
    East-West Design & Test Symposium (EWDTS 2013), 2013
    Co-Authors: Alexander Barkalov, Roman M. Babakov, Larysa Titarenko
    Abstract:

    The using of operational automaton of transitions as the block of microinstruction addressing of compositional Microprogram control unit is proposed. The new structure model of compositional Microprogram control unit with reduced hardware amount is developed. The generalized structure of operational automaton of transitions is suggested. An example of process of synthesis of compositional Microprogram control unit with operational automaton of transitions is given.

  • PDeS - Compositional Microprogram Control Unit with Operational Automaton of Transitions
    IFAC Proceedings Volumes, 2013
    Co-Authors: Alexander Barkalov, Roman M. Babakov, Larysa Titarenko
    Abstract:

    Abstract The using of operational automaton of transitions as the block of microinstruction addressing of compositional Microprogram control unit is proposed. The new structure model of compositional Microprogram control unit with reduced hardware amount is developed. The generalized structure of operational automaton of transitions is suggested. An example of process of synthesis of compositional Microprogram control unit with operational automaton of transitions is given.

  • compositional Microprogram control unit with operational automaton of transitions
    Programmable Devices and Embedded Systems, 2013
    Co-Authors: Alexander Barkalov, Roman M. Babakov, Larysa Titarenko
    Abstract:

    Abstract The using of operational automaton of transitions as the block of microinstruction addressing of compositional Microprogram control unit is proposed. The new structure model of compositional Microprogram control unit with reduced hardware amount is developed. The generalized structure of operational automaton of transitions is suggested. An example of process of synthesis of compositional Microprogram control unit with operational automaton of transitions is given.

  • logic synthesis for compositional Microprogram control units
    2010
    Co-Authors: Alexander Barkalov, Larysa Titarenko
    Abstract:

    The control unit is one of the most important parts of any digital system. As a rule, control units have an irregular structure, which makes the processing of their logic circuits design very sophisticated. One possible way to optimise such characteristics as the size or performance of control units is to adapt their structures to the particular properties of interpreted control algorithms. In this book control algorithms are represented by the linear graph-schemes of algorithms (GSA), where the number of operator vertices is not less than 75% of the total number of all algorithm vertices. A special class of control units named as compositional Microprogram control units (CMCU) is proposed as the best way for interpretation of linear control algorithms. The CMCU includes a finite state machine, which addresses microinstructions of interpreted Microprogram, and a Microprogram control unit including control memory, which keeps only microoperations of initial GSA. The Microprogram control unit uses the principle of natural addressing of microinstructions. Organization of the control unit proposed in the book increases regularity of the circuit, because the system of microoperations is implemented using standard blocks, such as PROM or RAM. At the same time, an irregular part of the system described by means of Boolean functions is reduced. It permits a decrease in the total number of logical elements (PAL, GAL, PLA, FPGA) in comparison with other models of finite state machines. The main goal of all proposed methods is reduction of the number of field-programmable logic devices used for implementation of logic circuit of the addressing FSM. This book will be interesting and useful for students and postgraduates in the area of Computer Science and for designers of modern digital devices. Compositional Microprogram control units enlarge the class of models applied for implementation of control units with modern field-programmable logic devices.

Patrick Van Der Smagt - One of the best experts on this subject based on the ideXlab platform.

  • CAS - Computer Systemen en Applicaties
    1994
    Co-Authors: Patrick Van Der Smagt
    Abstract:

    ion 6 high-level programming 5 imperative programming 4 assembly language 3 operating system kernel 2 machine language 1 Microprogram 0 digital logic Table 1.1: A possible anatomy of the modern digital computer (after (Tanenbaum, 1984)). dissection, as presented in the table, will not be unfamiliar or controversial to the initiated, the distinction between the levels is not as clear-cut as the table may suggest. There is one important difference, however, which may be regarded as a guideline: in general, the translation between the higher levels occurs through compilation; the translation among the lower levels through interpretation. That is to say, a Pascal program at level 5 will, in general, be compiled to level 4 before it is executed. On the other hand, a program at level 2 (in machine language) is actually interpreted in the Microprogram at level 1, instead of compiled. By dissecting a digital computer in such a way, this text will attempt to present a view of that computer whi..