The Experts below are selected from a list of 63702 Experts worldwide ranked by ideXlab platform
Ming Cheng - One of the best experts on this subject based on the ideXlab platform.
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A real time testing system for wind turbine controller with xPC Target Machine
International Journal of Electrical Power & Energy Systems, 2015Co-Authors: Jianzhong Zhang, Ming ChengAbstract:Abstract A cheap hardware-in-the-loop testing system for wind turbine controller is built based on MATLAB xPC. A wind-power generation model is constructed in the Matlab/Simulink of host Machine, where the code is generated by real-time workshop and downloaded to the Target Machine. Then the virtual wind power generation system may be controlled by the physical controller, and the effectiveness and performance of the controller can be validated. By composing the drivers for xPC device, the selection of I/O devices for the testing system is flexible. A friendly interface of the testing system is established by combination of xPC and virtual reality toolbox. A testing system for wind power generation system with friend interface may be established by the described method.
Charles C Weems - One of the best experts on this subject based on the ideXlab platform.
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generalized instruction selector generation the automatic construction of instruction selectors from descriptions of compiler internal forms and Target Machines
2010Co-Authors: Eliot J B Moss, Charles C Weems, Timothy RichardsAbstract:One of the most difficult tasks a compiler writer faces is the construction of the instruction selector. The instruction selector is that part of the compiler that translates compiler intermediate representation (IR) into instructions for a Target Machine. Unfortunately, implementing an instruction selector “by hand” is a difficult, time consuming, and error prone task. The details of both the IR and Target instruction set must be carefully considered in order to generate correct and efficient code. This, in turn, requires an expert in both the compiler internals as well as the Target Machine. Even an expert, however, can implement an instruction selector that is difficult to verify and debug. In this dissertation we describe the instruction selector problem, cover previous attempts at solving it, and identify what we believe to be the most prominent factor inhibiting their widespread adoption. This dissertation proposes a generalized approach toward generating instruction selectors automatically. In particular, we propose CISL, a common Machine description language for specifying the semantics of compiler IR and Target instructions, and GIST, a Machine independent heuristic search procedure that can find equivalent instruction sequences between compiler IR and Target instructions. CISL is an object-oriented-based language leveraging modern programming language constructs (e.g., classes, inheritance, mixins) and is capable of describing instructions for a variety of IR and Target ISAs (Instruction Set Architecture). GIST leverages CISLs well-defined semantics and a canonicalization process to discover automatically instruction selector patterns: Target instruction sequences that implement IR semantics. These instruction selector patterns are then generated in a compiler implementation independent format (XML). Small adapter programs use the generated instruction selector patterns to generate compiler specific implementation code. Our experiments show that instruction selector patterns can be discovered automatically and independent of a particular compiler framework or Target Machine. In addition, experience proved that adapter programs are easy to implement and instruction selector code is easy to generate from generated patterns. Furthermore, the generated instruction selectors are comparable in performance to the original compilers.
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IPDPS - Towards universal code generator generation
2008 IEEE International Symposium on Parallel and Distributed Processing, 2008Co-Authors: Timothy Richards, Edward K. Walters, Trek Palmer, J.e.b. Moss, Charles C WeemsAbstract:One of the most difficult tasks a compiler writer faces is the construction of the code generator. The code generator is that part of the compiler that translates compiler intermediate representation (IR) into instructions for a Target Machine. Unfortunately, implementing a code generator "by hand" is a difficult, time consuming, and error prone task. The details of both the IR and Target instruction set must be carefully considered in order to generate correct and efficient code. This, in turn, requires an expert in both the compiler internals as well as the Target Machine. Even an expert, however, can produce a code generator that is difficult to verify and debug. In this paper we present a universal approach for automating the construction of correct code generators. In particular, we show that both the compiler IR and Target instruction set semantics can be described by a Machine description language and leveraged by a heuristic search procedure to derive code generator patterns. We then utilize formal methods to determine if the IR and Target sequence pairs that make up these patterns are semantically equivalent.
Jean Peperstraete - One of the best experts on this subject based on the ideXlab platform.
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hardware software codesign with grape
Rapid System Prototyping, 1995Co-Authors: Rudy Lauwereins, Jean PeperstraeteAbstract:GRAPE-II (Graphical Rapid Prototyping Environment-II) is a hardware-software codesign environment for the real-time functional emulation of synchronous DSP systems. It allows one to specify the application's data dependency graph in a Target-Machine-independent way. After specifying the heterogeneous Target Machine's architecture, it estimates the resources needed by each application subtask. Based on these requirements, it assigns the subtasks to specific Target devices at compile-time, be they processors or FPGAs, establishes routing paths and determines a static schedule. It generates a main shell for each Target device and generates intra-device and inter-device communication code. After downloading the executable images on to the Target Machine, it allows the designer to modify end-user controls and application settings at run-time. This paper situates the tool in the application design cycle, explains GRAPE-II's design flow and shows the advantages of hardware-software codesign by evaluating the achievable sampling frequency for a small example application.
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RSP - Hardware-software codesign with GRAPE
Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype, 1995Co-Authors: Rudy Lauwereins, Jean PeperstraeteAbstract:GRAPE-II (Graphical Rapid Prototyping Environment-II) is a hardware-software codesign environment for the real-time functional emulation of synchronous DSP systems. It allows one to specify the application's data dependency graph in a Target-Machine-independent way. After specifying the heterogeneous Target Machine's architecture, it estimates the resources needed by each application subtask. Based on these requirements, it assigns the subtasks to specific Target devices at compile-time, be they processors or FPGAs, establishes routing paths and determines a static schedule. It generates a main shell for each Target device and generates intra-device and inter-device communication code. After downloading the executable images on to the Target Machine, it allows the designer to modify end-user controls and application settings at run-time. This paper situates the tool in the application design cycle, explains GRAPE-II's design flow and shows the advantages of hardware-software codesign by evaluating the achievable sampling frequency for a small example application.
Norman F. Ramsey - One of the best experts on this subject based on the ideXlab platform.
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CC - Converting intermediate code to assembly code using declarative Machine descriptions
Lecture Notes in Computer Science, 2006Co-Authors: João Rafael De Oliveira Dias, Norman F. RamseyAbstract:Writing an optimizing back end is expensive, in part because it requires mastery of both a Target Machine and a compiler's internals. We separate these concerns by isolating Target-Machine knowledge in declarative Machine descriptions. We then analyze these descriptions to automatically generate Machine-specific components of the back end. In this work, we generate a recognizer; this component, which identifies register transfers that correspond to Target-Machine instructions, plays a key role in instruction selection in such compilers as vpo, gcc and Quick C–. We present analyses and transformations that address the major challenge in generating a recognizer: accounting for compile-time abstractions not present in a Machine description, including variables, pseudo-registers, stack slots, and labels.
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CC - Widening Integer Arithmetic
Lecture Notes in Computer Science, 2004Co-Authors: Kevin Redwine, Norman F. RamseyAbstract:Some codes require computations to use fewer bits of precision than are normal for the Target Machine. For example, Java requires 32-bit arithmetic even on a 64-bit Target. To run narrow codes on a wide Target Machine, we present a widening transformation. Almost every narrow operation can be widened by sign- or zero-extending the operands and using a Target-Machine instruction at its natural width. But extensions can sometimes be avoided, and our transformation avoids as many as possible. The key idea is knowing what each operation can accept in the high bits of its arguments and what it can guarantee about the high bits of its result. This knowledge is formalized using fill types, which drive the widening transformation.
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A transformational approach to binary translation of delayed branches
ACM Transactions on Programming Languages and Systems, 2003Co-Authors: Norman F. Ramsey, Cristina CifuentesAbstract:A binary translator examines binary code for a source Machine and generates code for a Target Machine. Understanding what to do with delayed branches in binary code can involve tricky case analyses, for example, if there is a branch instruction in a delay slot. This article presents a disciplined method for deriving such case analyses. The method identifies problematic cases, shows the translations for the nonproblematic cases, and gives confidence that all cases are considered. The method supports such common architectures as SPARC, MIPS, and PA-RISC, and it should apply to any tool that analyzes Machine instructions. We begin by writing a very simple interpreter for the source Machine's code. We then transform the interpreter into an interpreter for a Target Machine without delayed branches. To maintain the semantics of the program being interpreted, we simultaneously transform the sequence of source-Machine instructions into a sequence of Target-Machine instructions. The transformation of the instructions becomes our algorithm for binary translation.
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A transformational approach to binary translation of delayed branches with applications to SPARC® and PA-RISC instructions sets
2002Co-Authors: Cristina Cifuentes, Norman F. RamseyAbstract:A binary translator examines binary code for a source Machine, optionally builds an intermediate representation, and generates code for a Target Machine. Understanding what to do with delayed branches in binary code can involve tricky case analyses, e.g., if there is a branch instruction in a delay slot. Correctness of a translation is of utmost importance. This paper presents a disciplined method for deriving such case analyses. The method identifies problematic cases, shows the translations for the non-problematic cases, and gives confidence that all cases are considered. The method supports such common architectures as SPARC®, MIPS, and PA-RISC. We begin by writing a very simple interpreter for the source Machine's code. We then transform the interpreter into an interpreter for a Target Machine without delayed branches. To maintain the semantics of the program being interpreted, we simultaneously transform the sequence of source-Machine instructions into a sequence of Target-Machine instructions. The transformation of the instructions becomes our algorithm for binary translation. We show the translation is correct by reasoning about corresponding states on source and Target Machines. Instantiation of this algorithm to the SPARC V8 and PA-RISC V1.1 architectures is shown. Of interest, these two Machines share seven of 11 classes of delayed branching semantics; the PA-RISC has three classes which are not available in the SPARC architecture, and the SPARC architecture has one class which is not available in the PA-RISC architecture. Although the delayed branch is an architectural idea whose time has come and gone, the method is significant to anyone who must write tools that deal with legacy binaries. For example, translators using this method could run PA-RISC on the new IA-64 architecture, or they may enable architects to eliminate delayed branches from a future version of the SPARC architecture.
Takeshi Kurata - One of the best experts on this subject based on the ideXlab platform.
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Mixed Reality Navigation on a Tablet Computer for Supporting Machine Maintenance in Wide-area Indoor Environment
2014Co-Authors: Koji Makita, Thomas Vincent, Soichi Ebisuno, Masakatsu Kourogi, Tomoya Ishikawa, Takashi Okuma, Minoru Yoshida, Laurence Nigay, Takeshi KurataAbstract:This paper describes a maintenance service support system for wide-area indoor environment, such as a factory and a hospital. In maintenance services, operators often have to check a map to find out a way to a Target Machine, and also have to refer documents to get information about check-up and repair of the Machine. In order to reduce working load of operators, information technology can help operators carry out additional but important operations during maintenance, such as referring documents and maps, recording maintenance logs and so on. In this paper, we propose mixed reality navigation on a tablet computer composed of augmented virtuality mode and augmented reality mode. Augmented virtuality mode performs map-based navigation shows positions of the user and the Target Machine. Augmented reality mode performs intuitive visualization of information about the Machine by overlaying annotations on camera images. The proposed system is based on a hybrid localization technique realized with pedestrian dead reckoning (PDR) and 3D model-based image processing for the purpose of covering wide-area indoor environment. Experimental results using our prototype with a mock-up model of a Machine are also described for showing feasibility of our concept in the paper.
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Mixed Reality Navigation on a Tablet Computer for Supporting Machine Maintenance in Wide-area Indoor Environment
2014Co-Authors: Koji Makita, Thomas Vincent, Soichi Ebisuno, Masakatsu Kourogi, Tomoya Ishikawa, Takashi Okuma, Minoru Yoshida, Laurence Nigay, Takeshi KurataAbstract:This paper describes a maintenance service support system for wide-area indoor environment, such as a factory and a hospital. In maintenance services, operators often have to check a map to find out a way to a Target Machine, and also have to refer documents to get information about check-up and repair of the Machine. In order to reduce working load of operators, information technology can help operators carry out additional but important operations during maintenance, such as referring documents and maps, recording maintenance logs and so on. In this paper, we propose mixed reality navigation on a tablet computer composed of augmented virtuality mode and augmented reality mode. Augmented virtuality mode performs map-based navigation shows positions of the user and the Target Machine. Augmented reality mode performs intuitive visualization of information about the Machine by overlaying annotations on camera images. The proposed system is based on a hybrid localization technique realized with pedestrian dead reckoning (PDR) and 3D model-based image processing for the purpose of covering wide-area indoor environment. Experimental results using our prototype with a mock-up model of a Machine are also described for showing feasibility of our concept in the paper.
