The Experts below are selected from a list of 71988 Experts worldwide ranked by ideXlab platform
Toshiro Hiramoto - One of the best experts on this subject based on the ideXlab platform.
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detailed analysis of Minimum Operation voltage of extraordinarily unstable cells in fully depleted silicon on buried oxide six transistor static random access memory
Japanese Journal of Applied Physics, 2015Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6? from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.
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statistical analysis of Minimum Operation voltage v min in fully depleted silicon on thin box sotb sram cells
IEEE Silicon Nanoelectronics Workshop, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (V min ) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and statistically analyzed. It is newly found that V min deviates from a normal distribution and follows a log-normal distribution. Furthermore, it is found that the behaviors of the worst V min are different from the median V min or static noise margin (SNM), indicating that cell stability of high density SRAM must be judged by the worst V min .
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comparison and distribution of Minimum Operation voltage in fully depleted silicon on thin buried oxide and bulk static random access memory cells
Japanese Journal of Applied Physics, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hidekazu Oda, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst Vmin of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of Vmin of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage Operation upon introducing SOTB, because of reduced VTH variability.
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ultralow voltage Operation of silicon on thin box sotb 2mbit sram down to 0 37 v utilizing adaptive back bias
Symposium on VLSI Circuits, 2013Co-Authors: Yoshiki Yamamoto, Tomoko Mizutani, Hideki Makiyama, Shiro Kamohara, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Toshiro HiramotoAbstract:We demonstrated record 0.37V Minimum Operation voltage (V min ) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (A VT ∼1.3 mVµm) and adaptive back biasing (ABB), V min was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
Yoshiki Yamamoto - One of the best experts on this subject based on the ideXlab platform.
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detailed analysis of Minimum Operation voltage of extraordinarily unstable cells in fully depleted silicon on buried oxide six transistor static random access memory
Japanese Journal of Applied Physics, 2015Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6? from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.
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statistical analysis of Minimum Operation voltage v min in fully depleted silicon on thin box sotb sram cells
IEEE Silicon Nanoelectronics Workshop, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (V min ) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and statistically analyzed. It is newly found that V min deviates from a normal distribution and follows a log-normal distribution. Furthermore, it is found that the behaviors of the worst V min are different from the median V min or static noise margin (SNM), indicating that cell stability of high density SRAM must be judged by the worst V min .
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comparison and distribution of Minimum Operation voltage in fully depleted silicon on thin buried oxide and bulk static random access memory cells
Japanese Journal of Applied Physics, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hidekazu Oda, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst Vmin of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of Vmin of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage Operation upon introducing SOTB, because of reduced VTH variability.
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ultralow voltage Operation of silicon on thin box sotb 2mbit sram down to 0 37 v utilizing adaptive back bias
Symposium on VLSI Circuits, 2013Co-Authors: Yoshiki Yamamoto, Tomoko Mizutani, Hideki Makiyama, Shiro Kamohara, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Toshiro HiramotoAbstract:We demonstrated record 0.37V Minimum Operation voltage (V min ) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (A VT ∼1.3 mVµm) and adaptive back biasing (ABB), V min was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
Tomoko Mizutani - One of the best experts on this subject based on the ideXlab platform.
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detailed analysis of Minimum Operation voltage of extraordinarily unstable cells in fully depleted silicon on buried oxide six transistor static random access memory
Japanese Journal of Applied Physics, 2015Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6? from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.
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statistical analysis of Minimum Operation voltage v min in fully depleted silicon on thin box sotb sram cells
IEEE Silicon Nanoelectronics Workshop, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (V min ) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and statistically analyzed. It is newly found that V min deviates from a normal distribution and follows a log-normal distribution. Furthermore, it is found that the behaviors of the worst V min are different from the median V min or static noise margin (SNM), indicating that cell stability of high density SRAM must be judged by the worst V min .
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comparison and distribution of Minimum Operation voltage in fully depleted silicon on thin buried oxide and bulk static random access memory cells
Japanese Journal of Applied Physics, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hidekazu Oda, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst Vmin of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of Vmin of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage Operation upon introducing SOTB, because of reduced VTH variability.
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ultralow voltage Operation of silicon on thin box sotb 2mbit sram down to 0 37 v utilizing adaptive back bias
Symposium on VLSI Circuits, 2013Co-Authors: Yoshiki Yamamoto, Tomoko Mizutani, Hideki Makiyama, Shiro Kamohara, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Toshiro HiramotoAbstract:We demonstrated record 0.37V Minimum Operation voltage (V min ) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (A VT ∼1.3 mVµm) and adaptive back biasing (ABB), V min was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
Nobuyuki Sugii - One of the best experts on this subject based on the ideXlab platform.
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detailed analysis of Minimum Operation voltage of extraordinarily unstable cells in fully depleted silicon on buried oxide six transistor static random access memory
Japanese Journal of Applied Physics, 2015Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6? from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.
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statistical analysis of Minimum Operation voltage v min in fully depleted silicon on thin box sotb sram cells
IEEE Silicon Nanoelectronics Workshop, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (V min ) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and statistically analyzed. It is newly found that V min deviates from a normal distribution and follows a log-normal distribution. Furthermore, it is found that the behaviors of the worst V min are different from the median V min or static noise margin (SNM), indicating that cell stability of high density SRAM must be judged by the worst V min .
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comparison and distribution of Minimum Operation voltage in fully depleted silicon on thin buried oxide and bulk static random access memory cells
Japanese Journal of Applied Physics, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hidekazu Oda, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst Vmin of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of Vmin of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage Operation upon introducing SOTB, because of reduced VTH variability.
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ultralow voltage Operation of silicon on thin box sotb 2mbit sram down to 0 37 v utilizing adaptive back bias
Symposium on VLSI Circuits, 2013Co-Authors: Yoshiki Yamamoto, Tomoko Mizutani, Hideki Makiyama, Shiro Kamohara, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Toshiro HiramotoAbstract:We demonstrated record 0.37V Minimum Operation voltage (V min ) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (A VT ∼1.3 mVµm) and adaptive back biasing (ABB), V min was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
Hideki Makiyama - One of the best experts on this subject based on the ideXlab platform.
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detailed analysis of Minimum Operation voltage of extraordinarily unstable cells in fully depleted silicon on buried oxide six transistor static random access memory
Japanese Journal of Applied Physics, 2015Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6? from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.
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statistical analysis of Minimum Operation voltage v min in fully depleted silicon on thin box sotb sram cells
IEEE Silicon Nanoelectronics Workshop, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Toshiro HiramotoAbstract:The Minimum Operation voltage (V min ) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and statistically analyzed. It is newly found that V min deviates from a normal distribution and follows a log-normal distribution. Furthermore, it is found that the behaviors of the worst V min are different from the median V min or static noise margin (SNM), indicating that cell stability of high density SRAM must be judged by the worst V min .
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comparison and distribution of Minimum Operation voltage in fully depleted silicon on thin buried oxide and bulk static random access memory cells
Japanese Journal of Applied Physics, 2014Co-Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hidekazu Oda, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Toshiro HiramotoAbstract:The Minimum Operation voltage (Vmin) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst Vmin of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of Vmin of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage Operation upon introducing SOTB, because of reduced VTH variability.
-
ultralow voltage Operation of silicon on thin box sotb 2mbit sram down to 0 37 v utilizing adaptive back bias
Symposium on VLSI Circuits, 2013Co-Authors: Yoshiki Yamamoto, Tomoko Mizutani, Hideki Makiyama, Shiro Kamohara, Nobuyuki Sugii, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Toshiro HiramotoAbstract:We demonstrated record 0.37V Minimum Operation voltage (V min ) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (A VT ∼1.3 mVµm) and adaptive back biasing (ABB), V min was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.