The Experts below are selected from a list of 162 Experts worldwide ranked by ideXlab platform

Hiroshi Nakamura - One of the best experts on this subject based on the ideXlab platform.

  • ISLPED - On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hideharu Amano, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

  • ISLPED - On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

  • On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

Biykem Bozkurt - One of the best experts on this subject based on the ideXlab platform.

  • delayed recovery in peripartum cardiomyopathy an indication for long term follow up and sustained therapy
    European Journal of Heart Failure, 2012
    Co-Authors: Murat Biteker, Erkan İlhan, Gul Biteker, Dursun Duman, Biykem Bozkurt
    Abstract:

    Aims Persistence of left ventricular (LV) systolic dysfunction after 6 months of diagnosis is believed to be a marker of an irreversible cardiomyopathy in peripartum cardiomyopathy (PPCM). We sought to determine the length of Time Required for recovery of LV systolic function (LVSF) in patients with PPCM. Methods and results Forty-two consecutive women with PPCM were enrolled in this prospective study. The Minimum Required Time of follow-up for inclusion was 30 months. Each patient underwent transthoracic echocardiography, and plasma brain natriuretic peptide (BNP) and C-reactive protein measurement at admission, and every 3 months. Early recovery was defined as normalization of LVSF at 6 months post-diagnosis. Delayed recovery was defined if the length of Time Required for recovery of LVSF was longer than 6 months. Persistent left ventricular dysfunction (PLVD) was defined as an ejection fraction of <50% at the end of follow-up. Twenty patients (47.6%) recovered completely, 10 died (23.8%), and 12 (28.6%) had PLVD. Average Time to complete recovery was 19.3 months after initial diagnosis (3–42 months). Early recovery was observed only in six patients (30%), whereas delayed recovery was observed in 14 out of 20 patients (70%). Patients with complete recovery were more likely to have a higher LV ejection fraction and smaller LV end-systolic dimensions at baseline. Conclusion Full recovery of LVSF in PPCM patients often requires longer than 6 months.

  • Delayed recovery in peripartum cardiomyopathy: an indication for long-term follow-up and sustained therapy.
    European journal of heart failure, 2012
    Co-Authors: Murat Biteker, Erkan İlhan, Gul Biteker, Dursun Duman, Biykem Bozkurt
    Abstract:

    Aims Persistence of left ventricular (LV) systolic dysfunction after 6 months of diagnosis is believed to be a marker of an irreversible cardiomyopathy in peripartum cardiomyopathy (PPCM). We sought to determine the length of Time Required for recovery of LV systolic function (LVSF) in patients with PPCM. Methods and results Forty-two consecutive women with PPCM were enrolled in this prospective study. The Minimum Required Time of follow-up for inclusion was 30 months. Each patient underwent transthoracic echocardiography, and plasma brain natriuretic peptide (BNP) and C-reactive protein measurement at admission, and every 3 months. Early recovery was defined as normalization of LVSF at 6 months post-diagnosis. Delayed recovery was defined if the length of Time Required for recovery of LVSF was longer than 6 months. Persistent left ventricular dysfunction (PLVD) was defined as an ejection fraction of

Kimiyoshi Usami - One of the best experts on this subject based on the ideXlab platform.

  • ISLPED - On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hideharu Amano, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

  • ISLPED - On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

  • On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

Murat Biteker - One of the best experts on this subject based on the ideXlab platform.

  • delayed recovery in peripartum cardiomyopathy an indication for long term follow up and sustained therapy
    European Journal of Heart Failure, 2012
    Co-Authors: Murat Biteker, Erkan İlhan, Gul Biteker, Dursun Duman, Biykem Bozkurt
    Abstract:

    Aims Persistence of left ventricular (LV) systolic dysfunction after 6 months of diagnosis is believed to be a marker of an irreversible cardiomyopathy in peripartum cardiomyopathy (PPCM). We sought to determine the length of Time Required for recovery of LV systolic function (LVSF) in patients with PPCM. Methods and results Forty-two consecutive women with PPCM were enrolled in this prospective study. The Minimum Required Time of follow-up for inclusion was 30 months. Each patient underwent transthoracic echocardiography, and plasma brain natriuretic peptide (BNP) and C-reactive protein measurement at admission, and every 3 months. Early recovery was defined as normalization of LVSF at 6 months post-diagnosis. Delayed recovery was defined if the length of Time Required for recovery of LVSF was longer than 6 months. Persistent left ventricular dysfunction (PLVD) was defined as an ejection fraction of <50% at the end of follow-up. Twenty patients (47.6%) recovered completely, 10 died (23.8%), and 12 (28.6%) had PLVD. Average Time to complete recovery was 19.3 months after initial diagnosis (3–42 months). Early recovery was observed only in six patients (30%), whereas delayed recovery was observed in 14 out of 20 patients (70%). Patients with complete recovery were more likely to have a higher LV ejection fraction and smaller LV end-systolic dimensions at baseline. Conclusion Full recovery of LVSF in PPCM patients often requires longer than 6 months.

  • Delayed recovery in peripartum cardiomyopathy: an indication for long-term follow-up and sustained therapy.
    European journal of heart failure, 2012
    Co-Authors: Murat Biteker, Erkan İlhan, Gul Biteker, Dursun Duman, Biykem Bozkurt
    Abstract:

    Aims Persistence of left ventricular (LV) systolic dysfunction after 6 months of diagnosis is believed to be a marker of an irreversible cardiomyopathy in peripartum cardiomyopathy (PPCM). We sought to determine the length of Time Required for recovery of LV systolic function (LVSF) in patients with PPCM. Methods and results Forty-two consecutive women with PPCM were enrolled in this prospective study. The Minimum Required Time of follow-up for inclusion was 30 months. Each patient underwent transthoracic echocardiography, and plasma brain natriuretic peptide (BNP) and C-reactive protein measurement at admission, and every 3 months. Early recovery was defined as normalization of LVSF at 6 months post-diagnosis. Delayed recovery was defined if the length of Time Required for recovery of LVSF was longer than 6 months. Persistent left ventricular dysfunction (PLVD) was defined as an ejection fraction of

Kensaku Matsunaga - One of the best experts on this subject based on the ideXlab platform.

  • ISLPED - On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hideharu Amano, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

  • ISLPED - On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

  • On-chip detection methodology for break-even Time of power gated function units
    IEEE ACM International Symposium on Low Power Electronics and Design, 2011
    Co-Authors: Kimiyoshi Usami, Kensaku Matsunaga, Yuya Goto, Daisuke Ikebuchi, Satoshi Koyama, Hiroshi Nakamura
    Abstract:

    In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the Minimum Required Time i.e. the break-even Time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.