The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Deming Chen - One of the best experts on this subject based on the ideXlab platform.
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flexible transition metal dichalcogenide field effect transistors a circuit level simulation study of delay and power under bending Process Variation and scaling
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Yingyu Chen, Morteza Gholipour, Deming ChenAbstract:In this paper, a new and efficient SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed for different types of materials, considering effects when scaling the transistor size down to the 16-nm technology node. Extensive circuit-level simulations are performed using this model, and the delay and power performance of TMDFET circuits with different amounts of bending are reported. Simulation results indicate that delay and power tradeoff can be done in TMDFET circuits via bending. Effects from Process Variation are also evaluated via circuit simulations. Finally, our cross-technology and scaling studies show that while TMDFETs perform better than Si-based transistors in terms of energy-delay product (EDP) at 180-nm and 90-nm technology nodes (the best being 12.7% and 40.7% of that of Si-based transistors, respectively), their EDPs are worse than Si-based transistors (at least 4.9× of that of the best performing Si-based transistor) on the 16-nm technology node. Such a compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes.
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a spice compatible model of mos type graphene nano ribbon field effect transistors enabling gate and circuit level delay and power analysis under Process Variation
IEEE Transactions on Nanotechnology, 2015Co-Authors: Yingyu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Morteza Gholipour, Deming ChenAbstract:This paper presents the first parameterized SPICE-compatible compact model of a graphene nano-ribbon field-effect transistor (GNRFET) with doped reservoirs, also known as MOS-type GNRFET. The current and charge models closely match numerical TCAD simulations. In addition, Process Variation in transistor dimension, line edge roughness, and doping level in the reservoirs are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under Process Variation, and offers design and fabrication insights for graphene circuits in the future. We show that line edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.
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schottky barrier type graphene nano ribbon field effect transistors a study on compact modeling Process Variation and circuit performance
International Symposium on Nanoscale Architectures, 2013Co-Authors: Yingyu Chen, Amit Sangai, Morteza Gholipour, Deming ChenAbstract:Graphene Nano-Ribbon Field-Effect Transistors (GNR-FETs) have emerged as promising next-generation devices. In particular, Schottky-barrier-type GNRFETs (SB-GNRFETs) have piqued interest due to their ambipolar I-V characteristics. Despite manufacturing successes, the lack of a SPICE-compatible compact model of SB-GNRFETs has hindered studies on evaluating the performance of this emerging technology on the circuit level. In this paper, we present the first SPICE-compatible model of SB-GNRFETs that takes various design parameters into account, which not only enables circuit-level simulations, but also provides a means to evaluate Process Variation, including effects of channel length, transistor width, oxide thickness, and graphene-specific edge roughness. With this model, we are able to explore the design space of SB-GNRFETs, evaluate delay and power performance of SB-GNRFET circuits, and compare them with conventional Si-CMOS and Metal-Oxide-Semiconductor-(MOS-)GNRFETs. Our study shows that SB-GNRFETs have higher speed and higher power dissipation, and have lower energy delay product than both Si-CMOS and MOS-GNRFETs, while MOS-GNRFETs are potentially good for low-power applications despite the presence of graphene-metal contact resistance that are not present in SB-GNRFET circuits. Two practical factors severely degrade the performance and even affect the functionality of SB-GNRFET circuits: 1) edge roughness and 2) limitation on operating point shifting.
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a spice compatible model of graphene nano ribbon field effect transistors enabling circuit level delay and power analysis under Process Variation
Design Automation and Test in Europe, 2013Co-Authors: Yingyu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Deming ChenAbstract:This paper presents the first parameterized, SPICE-compatible compact model of a Graphene Nano-Ribbon Field-Effect Transistor (GNRFET) with doped reservoirs that also supports Process Variation. The current and charge models closely match numerical TCAD simulations. In addition, Process Variation in transistor dimension, edge roughness, and doping level in the reservoir are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under Process Variation, and offers design and fabrication insights for graphene circuits in the future. We show that edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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ultralow voltage Process Variation tolerant schmitt trigger based sram design
IEEE Transactions on Very Large Scale Integration Systems, 2012Co-Authors: Jaydeep P Kulkarni, Kaushik RoyAbstract:We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving Process Variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.
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a voltage scalable Process Variation resilient hybrid sram architecture for mpeg 4 video Processors
Design Automation Conference, 2009Co-Authors: Ik Joon Chang, Debabrata Mohapatra, Kaushik RoyAbstract:We present a voltage-scalable and Process-Variation resilient memory architecture, suitable for MPEG-4 video Processors such that power dissipation can be traded for graceful degradation in "quality". The key innovation in our proposed work is a hybrid memory array, which is mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that human visual system (HVS) is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show average power savings of up to 56%, in the hybrid memory array compared to the conventional 6T SRAM array implemented in 65nm CMOS. The area overhead and maximum output quality degradation (PSNR) incurred were 11.5% and 0.56 dB, respectively.
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a high sensitivity Process Variation sensor utilizing sub threshold operation
Custom Integrated Circuits Conference, 2008Co-Authors: Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P Kulkarni, Kaushik RoyAbstract:In this paper, we propose a novel low-power, bias-free, high-sensitivity Process Variation sensor for monitoring random Variations in the threshold voltage. The proposed sensor design utilizes the exponential current-voltage relationship of sub-threshold operation thereby improving the sensitivity by 2.3X compared to the above-threshold operation. A test-chip containing 128 PMOS and 128 NMOS devices has been fabricated in 65 nm bulk CMOS Process technology. A total of 28 dies across the wafer have been fully characterized to determine the random threshold voltage Variations.
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Process Variation tolerant sram array for ultra low voltage applications
Design Automation Conference, 2008Co-Authors: Jaydeep P Kulkarni, Keejong Kim, Sang Phill Park, Kaushik RoyAbstract:In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better write- ability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving Process Variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130 nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher write- trip-point and 120 mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.
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Process Variation in embedded memories failure analysis and Variation aware architecture
Custom Integrated Circuits Conference, 2005Co-Authors: Amit Agarwal, Bipul C Paul, Saibal Mukhopadhyay, Kaushik RoyAbstract:With scaling of device dimensions, microscopic Variations in number and location of dopant atoms in the channel region of the device induce increasingly limiting electrical deviations in device characteristics such as threshold voltage. These atomic-level intrinsic fluctuations cannot be eliminated by external control of the manufacturing Process and are most pronounced in minimum-geometry transistors commonly used in area-constrained circuits such as SRAM cells. Consequently, a large number of cells in a memory are expected to be faulty due to Process Variations in sub-50-nm technologies. This paper analyzes SRAM cell failures under Process Variation and proposes new Variation-aware cache architecture suitable for high performance applications. The proposed architecture adaptively resizes the cache to avoid faulty cells, thereby improving yield. This scheme is transparent to Processor architecture and has negligible energy and area overhead. Experimental results on a 32 K direct map L1 cache show that the proposed architecture can achieve 93% yield compared to its original 33%. The- Simplescalar simulation shows that designing the data and instruction cache using the proposed architecture results in 1.5% and 5.7% average CPU performance loss (over SPEC 2000 benchmarks), respectively, for the chips with maximum number of faulty cells which can be tolerated by our proposed scheme.
Yingyu Chen - One of the best experts on this subject based on the ideXlab platform.
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flexible transition metal dichalcogenide field effect transistors a circuit level simulation study of delay and power under bending Process Variation and scaling
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Yingyu Chen, Morteza Gholipour, Deming ChenAbstract:In this paper, a new and efficient SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed for different types of materials, considering effects when scaling the transistor size down to the 16-nm technology node. Extensive circuit-level simulations are performed using this model, and the delay and power performance of TMDFET circuits with different amounts of bending are reported. Simulation results indicate that delay and power tradeoff can be done in TMDFET circuits via bending. Effects from Process Variation are also evaluated via circuit simulations. Finally, our cross-technology and scaling studies show that while TMDFETs perform better than Si-based transistors in terms of energy-delay product (EDP) at 180-nm and 90-nm technology nodes (the best being 12.7% and 40.7% of that of Si-based transistors, respectively), their EDPs are worse than Si-based transistors (at least 4.9× of that of the best performing Si-based transistor) on the 16-nm technology node. Such a compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes.
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a spice compatible model of mos type graphene nano ribbon field effect transistors enabling gate and circuit level delay and power analysis under Process Variation
IEEE Transactions on Nanotechnology, 2015Co-Authors: Yingyu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Morteza Gholipour, Deming ChenAbstract:This paper presents the first parameterized SPICE-compatible compact model of a graphene nano-ribbon field-effect transistor (GNRFET) with doped reservoirs, also known as MOS-type GNRFET. The current and charge models closely match numerical TCAD simulations. In addition, Process Variation in transistor dimension, line edge roughness, and doping level in the reservoirs are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under Process Variation, and offers design and fabrication insights for graphene circuits in the future. We show that line edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.
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schottky barrier type graphene nano ribbon field effect transistors a study on compact modeling Process Variation and circuit performance
International Symposium on Nanoscale Architectures, 2013Co-Authors: Yingyu Chen, Amit Sangai, Morteza Gholipour, Deming ChenAbstract:Graphene Nano-Ribbon Field-Effect Transistors (GNR-FETs) have emerged as promising next-generation devices. In particular, Schottky-barrier-type GNRFETs (SB-GNRFETs) have piqued interest due to their ambipolar I-V characteristics. Despite manufacturing successes, the lack of a SPICE-compatible compact model of SB-GNRFETs has hindered studies on evaluating the performance of this emerging technology on the circuit level. In this paper, we present the first SPICE-compatible model of SB-GNRFETs that takes various design parameters into account, which not only enables circuit-level simulations, but also provides a means to evaluate Process Variation, including effects of channel length, transistor width, oxide thickness, and graphene-specific edge roughness. With this model, we are able to explore the design space of SB-GNRFETs, evaluate delay and power performance of SB-GNRFET circuits, and compare them with conventional Si-CMOS and Metal-Oxide-Semiconductor-(MOS-)GNRFETs. Our study shows that SB-GNRFETs have higher speed and higher power dissipation, and have lower energy delay product than both Si-CMOS and MOS-GNRFETs, while MOS-GNRFETs are potentially good for low-power applications despite the presence of graphene-metal contact resistance that are not present in SB-GNRFET circuits. Two practical factors severely degrade the performance and even affect the functionality of SB-GNRFET circuits: 1) edge roughness and 2) limitation on operating point shifting.
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a spice compatible model of graphene nano ribbon field effect transistors enabling circuit level delay and power analysis under Process Variation
Design Automation and Test in Europe, 2013Co-Authors: Yingyu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Deming ChenAbstract:This paper presents the first parameterized, SPICE-compatible compact model of a Graphene Nano-Ribbon Field-Effect Transistor (GNRFET) with doped reservoirs that also supports Process Variation. The current and charge models closely match numerical TCAD simulations. In addition, Process Variation in transistor dimension, edge roughness, and doping level in the reservoir are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under Process Variation, and offers design and fabrication insights for graphene circuits in the future. We show that edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.
S Borkar - One of the best experts on this subject based on the ideXlab platform.
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on die cmos leakage current sensor for measuring Process Variation in sub 90nm generations
Symposium on VLSI Circuits, 2004Co-Authors: Chris H Kim, Kaushik Roy, Steven K Hsu, Ram Krishnamurthy, S BorkarAbstract:This paper describes an on-die leakage current sensor in 1.2V, 90nm CMOS technology for accurately measuring Process Variation. Results based on measured leakage data show (i) higher signal-to-noise ratio and (ii) reduced sensitivity to supply and P/N skew Variations compared to prior designs, while the proposed sensor only requires a single bias generator even for multi-bit resolution sensing. A 6-channel leakage current monitor testchip fabricated in 90nm dual-Vt CMOS is also described.
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a Process Variation compensating technique for sub 90 nm dynamic circuits
Symposium on VLSI Circuits, 2003Co-Authors: Chris H Kim, Kaushik Roy, S Hsu, Atila Alvandpour, R K Krishnamurthy, S BorkarAbstract:A Process Variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage Variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay Variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.
Weiping Shi - One of the best experts on this subject based on the ideXlab platform.
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longest path selection for delay test under Process Variation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005Co-Authors: Wangqi Qiu, D M H Walker, Weiping ShiAbstract:Under manufacturing Process Variation, a path through a net is called longest if there exists a Process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different Process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To detect delay faults due to local defects and Process Variation, it is necessary to test all longest paths through each net. Previous approaches to this problem were inefficient because of the large number of paths that are not longest. This paper presents an efficient method to generate the set of longest paths for delay test under Process Variation. To capture both structural and Process correlation between path delays, we use linear delay functions to express path delays under Process Variation. A novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths. In experiments on International Symposium on Circuits and Systems (ISCAS) circuits, our number of longest paths is 1-6% of the previous best approach, with 300/spl times/ less running time.
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longest path selection for delay test under Process Variation
Asia and South Pacific Design Automation Conference, 2004Co-Authors: Wangqi Qiu, D M H Walker, Weiping ShiAbstract:Under manufacturing Process Variation, a path through a fault site is called longest for delay test if there exists a Process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different Process conditions. To detect the smallest delay fault, it is necessary to test all longest paths through the fault site. However, previous methods are either inefficient or their results include too many paths that are not longest.This paper presents an efficient method to generate the longest path set for delay test under Process Variation. To capture both structural and systematic Process correlation, we use linear delay functions to express path delays under Process Variation. A novel path-pruning technique is proposed to discard paths that are not longest, resulting in a significantly reduction in the number of paths compared with the previous best method. The new method can be applied to any Process Variation as long as its impact on delay is linear.
