The Experts below are selected from a list of 399 Experts worldwide ranked by ideXlab platform
Brian Todd Kelley - One of the best experts on this subject based on the ideXlab platform.
-
On the rapid prototyping and design of a wireless communication system on a chip
1999 IEEE ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), 1Co-Authors: Brian Todd KelleyAbstract:Summary form only given. The evolutionary convergence of computing, integrated circuit technology, and advances in wireless communications has led to an explosive growth of personal communication devices and services (PCS). In fact, the dramatic "Moores Law" shrinkage of IC devices, itself, has led to an unprecedented ability to place increasingly complex systems on a chip (SoC).
Jason T. Stauth - One of the best experts on this subject based on the ideXlab platform.
-
Efficient Voltage Regulation for Microprocessor Cores Stacked in Vertical Voltage Domains
IEEE Transactions on Power Electronics, 2016Co-Authors: Christopher Schaef, Jason T. StauthAbstract:Due to exponential (Moores Law) scaling of advanced CMOS technologies, the challenges associated with delivering power to performance and mobile computing systems are outpacing the capabilities of conventional voltage regulator (VR) topologies. To continue to scale throughput at constant power density, the level of parallelism in microprocessor architectures is expected to increase substantially. In this paper, we present a power conversion topology to provide independent multicore regulation in the 0.8–1.4 V range from a 12-V dc bus. The topology uses a multistage ladder converter to manage power delivery to digital circuits stacked in vertical voltage domains. This approach has several advantages with regard to systems efficiency as it allows a more moderate conversion ratio of the main dc–dc converter. Moreover, the parallel converter only needs to process a fraction of the power of each core as the current can be “recycled” by adjacent cores in the stack. We develop a dynamical model for a multiple-input, multiple-output control scheme that uses a simple integral-control Law, augmented with fast voltage- and current-mode feedforward. Measurement results of a discrete prototype verify the control scheme and demonstrate the potential advantages in system efficiency but also emphasize the remaining challenges in meeting stringent VR dynamic response requirements.
Roberth Munnig Schmidt - One of the best experts on this subject based on the ideXlab platform.
-
ultra precision engineering in lithographic exposure equipment for the semiconductor industry
Philosophical Transactions of the Royal Society A, 2012Co-Authors: Roberth Munnig SchmidtAbstract:The developments in lithographic tools for the production of an integrated circuit (IC) are ruled by Moores Law: the density of components on an IC doubles in about every two years. The correspondi...
Miranda Cupertino - One of the best experts on this subject based on the ideXlab platform.
-
Erbium : réconcilier les langages, les supports d'exécution, la compilation, et les optimisations pour calculs sur des flux de données
HAL CCSD, 2013Co-Authors: Miranda CupertinoAbstract:As transistors size and power limitations stroke computer industry, hardware parallelism arose as the solution, bringing old forgotten problems back into equation to solve the existing limitations of current parallel technologies. Compilers regain focus by being the most relevant puzzle piece in the quest for the expected computer performance improvements predicted by Moores Law no longer possible without parallelism. Parallel research is mainly focused in either the language or architectural aspects, not really giving the needed attention to compiler problems, being the reason for the weak compiler support by many parallel languages or architectures, not allowing to exploit performance to the best. This thesis addresses these problems by presenting: Erbium, a low level streaming data-flow language supporting multiple producer and consumer task communication; a very efficient runtime implementation for x86 architectures also addressing other types of architectures; a compiler integration of the language as an intermediate representation in GCC; a study of the language primitives dependencies, allowing compilers to further optimise the Erbium code not only through specific parallel optimisations but also through traditional compiler optimisations, such as partial redundancy elimination and dead code elimination.Frappée par les rendements décroissants de la performance séquentielle et les limitations thermiques, l’industrie des microprocesseurs s’est tournée résolument vers les multiprocesseurs sur puce. Ce mouvement a ramené des problèmes anciens et difficiles sous les feux de l’actualité du développement logiciel. Les compilateurs sont l’une des pièces maitresses du puzzle permettant de poursuivre la traduction de la loi de Moore en gains de performances effectifs, gains inaccessibles sans exploiter le parallélisme de threads. Pourtant, la recherche sur les systèmes parallèles s’est concentrée sur les aspects langage et architecture, et le potentiel reste énorme en termes de compilation de programmes parallèles, d’optimisation et d’adaptation de programmes parallèles pour exploiter efficacement le matériel. Cette thèse relève ces défis en présentant Erbium, un langage de bas niveau fondé sur le traitement de flots de données, et mettant en œuvre des communications multi-producteur multi-consommateur ; un exécutif parallèle très efficace pour les architectures x86 et des variantes pour d’autres types d’architectures ; un schéma d’intégration du langage dans un compilateur illustré en tant que représentation intermédiaire dans GCC ; une étude des primitives du langage et de leurs dépendances permettant aux compilateurs d’optimiser des programmes Erbium à l’aide de transformations spécifiques aux programmes parallèles, et également à travers des formes généralisées d’optimisations classiques, telles que l’élimination de redondances partielles et l’élimination de code mort
-
Erbium (réconcilier les langages, les supports d'exécution, la compilation, et les optimisations pour calculs sur des flux de données)
2013Co-Authors: Miranda Cupertino, Cohen, Albert HenriAbstract:Frappée par les rendements décroissants de la performance séquentielle et les limitations thermiques, l industrie des microprocesseurs s est tournée résolument vers les multiprocesseurs sur puce. Ce mouvement a ramené des problèmes anciens et difficiles sous les feux de l actualité du développement logiciel. Les compilateurs sont l une des pièces maitresses du puzzle permettant de poursuivre la traduction de la loi de Moore en gains de performances effectifs, gains inaccessibles sans exploiter le parallélisme de threads. Pourtant, la recherche sur les systèmes parallèles s est concentrée sur les aspects langage et architecture, et le potentiel reste énorme en termes de compilation de programmes parallèles, d optimisation et d adaptation de programmes parallèles pour exploiter efficacement le matériel. Cette thèse relève ces défis en présentant Erbium, un langage de bas niveau fondé sur le traitement de flots de données, et mettant en œuvre des communications multi-producteur multi-consommateur ; un exécutif parallèle très efficace pour les architectures x86 et des variantes pour d autres types d architectures ; un schéma d intégration du langage dans un compilateur illustré en tant que représentation intermédiaire dans GCC ; une étude des primitives du langage et de leurs dépendances permettant aux compilateurs d optimiser des programmes Erbium à l aide de transformations spécifiques aux programmes parallèles, et également à travers des formes généralisées d optimisations classiques, telles que l élimination de redondances partielles et l élimination de code mort.As transistors size and power limitations stroke computer industry, hardware parallelism arose as the solution, bringing old forgotten problems back into equation to solve the existing limitations of current parallel technologies. Compilers regain focus by being the most relevant puzzle piece in the quest for the expected computer performance improvements predicted by Moores Law no longer possible without parallelism. Parallel research is mainly focused in either the language or architectural aspects, not really giving the needed attention to compiler problems, being the reason for the weak compiler support by many parallel languages or architectures, not allowing to exploit performance to the best. This thesis addresses these problems by presenting: Erbium, a low level streaming data-flow language supporting multiple producer and consumer task communication; a very efficient runtime implementation for x86 architectures also addressing other types of architectures; a compiler integration of the language as an intermediate representation in GCC; a study of the language primitives dependencies, allowing compilers to further optimise the Erbium code not only through specific parallel optimisations but also through traditional compiler optimisations, such as partial redundancy elimination and dead code elimination.PARIS11-SCD-Bib. électronique (914719901) / SudocSudocFranceF
Christopher Schaef - One of the best experts on this subject based on the ideXlab platform.
-
Efficient Voltage Regulation for Microprocessor Cores Stacked in Vertical Voltage Domains
IEEE Transactions on Power Electronics, 2016Co-Authors: Christopher Schaef, Jason T. StauthAbstract:Due to exponential (Moores Law) scaling of advanced CMOS technologies, the challenges associated with delivering power to performance and mobile computing systems are outpacing the capabilities of conventional voltage regulator (VR) topologies. To continue to scale throughput at constant power density, the level of parallelism in microprocessor architectures is expected to increase substantially. In this paper, we present a power conversion topology to provide independent multicore regulation in the 0.8–1.4 V range from a 12-V dc bus. The topology uses a multistage ladder converter to manage power delivery to digital circuits stacked in vertical voltage domains. This approach has several advantages with regard to systems efficiency as it allows a more moderate conversion ratio of the main dc–dc converter. Moreover, the parallel converter only needs to process a fraction of the power of each core as the current can be “recycled” by adjacent cores in the stack. We develop a dynamical model for a multiple-input, multiple-output control scheme that uses a simple integral-control Law, augmented with fast voltage- and current-mode feedforward. Measurement results of a discrete prototype verify the control scheme and demonstrate the potential advantages in system efficiency but also emphasize the remaining challenges in meeting stringent VR dynamic response requirements.