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Mohamed Benromdhane - One of the best experts on this subject based on the ideXlab platform.

  • constraint driven bus matrix synthesis for mpsoc
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full bus matrix and up to 3.2 X savings when compared to a maximally connected reduced bus matrix.

  • constraint driven bus matrix synthesis for mpsoc
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel buses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9/spl times/ component savings when compared to a full bus matrix and up to 3.2/spl times/ savings when compared to a maximally connected reduced bus matrix.

Sudeep Pasricha - One of the best experts on this subject based on the ideXlab platform.

  • constraint driven bus matrix synthesis for mpsoc
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full bus matrix and up to 3.2 X savings when compared to a maximally connected reduced bus matrix.

  • constraint driven bus matrix synthesis for mpsoc
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel buses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9/spl times/ component savings when compared to a full bus matrix and up to 3.2/spl times/ savings when compared to a maximally connected reduced bus matrix.

Nikil Dutt - One of the best experts on this subject based on the ideXlab platform.

  • constraint driven bus matrix synthesis for mpsoc
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full bus matrix and up to 3.2 X savings when compared to a maximally connected reduced bus matrix.

  • constraint driven bus matrix synthesis for mpsoc
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel buses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9/spl times/ component savings when compared to a full bus matrix and up to 3.2/spl times/ savings when compared to a maximally connected reduced bus matrix.

Francois Gindraud - One of the best experts on this subject based on the ideXlab platform.

  • distributed runtime system with global address space and software cache coherence for a data flow task model
    2018
    Co-Authors: Francois Gindraud
    Abstract:

    Distributed systems are widely used in HPC (High Performance Computing). Owing to rising energy concerns, some chip manufacturers moved from multi-core CPUs to MPSoC (multi-processor System on Chip), which includes a distributed system on one chip.However distributed systems – with distributed memories – are hard to program compared to more friendly shared memory systems. A family of solutions called DSM (Distributed Shared Memory) systems has been developed to simplify the programming of distributed systems. DSM systems include NUMA architectures, PGAS languages, and distributed task runtimes. The common strategy of these systems is to create a global address space of some kind, and automate network transfers on accesses to global objects. DSM systems usually differ in their interfaces, capabilities, semantics on global objects, implementation levels (hardware / software), ...This thesis presents a new software DSM system called Givy. The motivation of Givy is to execute programs modeled as dynamic task graphs with data-flow dependencies on MPSoC architectures (MPPA). Contrary to many software DSM, the global address space of Givy is indexed by real pointers: raw C pointers are made global to the distributed system. Givy global objects are memory blocks returned by malloc(). Data is replicated across nodes, and all these copies are managed by a software cache coherence protocol called Owner Writable Memory. This protocol can relocate coherence metadata, and thus should help execute irregular applications efficiently. The programming model cuts the program into tasks which are annotated with memory accesses, and created dynamically. Memory annotations are used to drive coherence requests, and provide useful information for scheduling and load-balancing.The first contribution of this thesis is the overall design of the Givy runtime. A second contribution is the formalization of the Owner Writable Memory coherence protocol. A third contribution is its translation in a model checker language (Cubicle), and correctness validation attempts. The last contribution is the detailed allocator subsystem implementation: the choice of real pointers for global references requires a tight integration between memory allocator and coherence protocol.

  • an interval constrained memory allocator for the givy gas runtime
    ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016
    Co-Authors: Francois Gindraud, Fabrice Rastello, Albert Cohen, Francois Broquedis
    Abstract:

    The shared memory model helps parallel programming productivity, but it also has a high hardware cost and imposes scalability constraints. Ultimately, higher performance will use distributed memories, which scales better but requires programmers to manually transfer data between local memories, which is a complex task. Distributed memories are also more energy efficient than shared memories, and are used in a family of embedded computing solutions called multi processor system on chip (MPSoC).

Giard Pascal - One of the best experts on this subject based on the ideXlab platform.

  • A Standalone FPGA-Based Miner for Lyra2REv2 Cryptocurrencies
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Tetu Jean-francois, Trudeau Louis-charles, Van Beirendonck Michiel, Balatsoukas-stimming Alexios, Giard Pascal
    Abstract:

    Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2. Several properties of the aforementioned algorithm are exploited in order to optimize the design. In addition, an FPGA-based hardware implementation of a standalone miner for Lyra2REv2 on a Xilinx multi-processor System on Chip is presented. The proposed Lyra2REv2 miner is shown to be significantly more energy efficient than both a GPU and a commercially available FPGA-based miner. Finally, we also explain how the simplified Lyra2 and Lyra2REv2 architectures can be modified with minimal effort to also support the recent Lyra2REv3 chained hashing algorithm

  • A Standalone FPGA-Based Miner for Lyra2REv2 Cryptocurrencies
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Tetu, Jean Francois, Van Beirendonck Michiel, Balatsoukas-stimming Alexios, Trudeau, Louis Charles, Giard Pascal
    Abstract:

    \u3cp\u3eLyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2. Several properties of the aforementioned algorithm are exploited in order to optimize the design. In addition, an FPGA-based hardware implementation of a standalone miner for Lyra2REv2 on a Xilinx multi-processor System on Chip is presented. The proposed Lyra2REv2 miner is shown to be significantly more energy efficient than both a GPU and a commercially available FPGA-based miner. Finally, we also explain how the simplified Lyra2 and Lyra2REv2 architectures can be modified with minimal effort to also support the recent Lyra2REv3 chained hashing algorithm.\u3c/p\u3

  • A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies
    2020
    Co-Authors: Tetu Jean-francois, Trudeau Louis-charles, Van Beirendonck Michiel, Balatsoukas-stimming Alexios, Giard Pascal
    Abstract:

    Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2. Several properties of the aforementioned algorithm are exploited in order to optimize the design. In addition, an FPGA-based hardware implementation of a standalone miner for Lyra2REv2 on a Xilinx multi-processor System on Chip is presented. The proposed Lyra2REv2 miner is shown to be significantly more energy efficient than both a GPU and a commercially available FPGA-based miner. Finally, we also explain how the simplified Lyra2 and Lyra2REv2 architectures can be modified with minimal effort to also support the recent Lyra2REv3 chained hashing algorithm.Comment: 13 pages, accepted for publication in IEEE Trans. Circuits Syst. I. arXiv admin note: substantial text overlap with arXiv:1807.0576