The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform
Y Nakagome - One of the best experts on this subject based on the ideXlab platform.
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
IEEE Journal of Solid-state Circuits, 1995Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
Custom Integrated Circuits Conference, 1994Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-/spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77 mm/spl times/3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply. >
N Ohkubo - One of the best experts on this subject based on the ideXlab platform.
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
IEEE Journal of Solid-state Circuits, 1995Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
Custom Integrated Circuits Conference, 1994Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-/spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77 mm/spl times/3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply. >
Robert R Tucci - One of the best experts on this subject based on the ideXlab platform.
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code generator for quantum simulated annealing
arXiv: Quantum Physics, 2009Co-Authors: Robert R TucciAbstract:This paper introduces QuSAnn v1.2 and Multiplexor Expander v1.2, two Java applications available for free. (Source code included in the distribution.) QuSAnn is a \code generator" for quantum simulated annealing: after the user inputs some parameters, it outputs a quantum circuit for performing simulated annealing on a quantum computer. The quantum circuit implements the algorithm of Wocjan et al. (arXiv:0804.4259), which improves on the original algorithm of Somma et al. (arXiv:0712.1008). The quantum circuit generated by QuSAnn includes some quantum Multiplexors. The application Multiplexor Expander allows the user to replace each of those Multiplexors by a sequence of more elementary gates such as multiply controlled NOTs and qubit rotations.
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oracular approximation of quantum Multiplexors and diagonal unitary matrices
arXiv: Quantum Physics, 2009Co-Authors: Robert R TucciAbstract:We give a new quantum circuit approximation of quantum Multiplexors based on the idea of complexity theory oracles. As an added bonus, our multiplexor approximation immediately gives a quantum circuit approximation of diagonal unitary matrices.
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Oracular Approximation of Quantum Multiplexors and Diagonal Unitary Matrices
2009Co-Authors: Robert R TucciAbstract:We give a new quantum circuit approximation for quantum Multiplexors based on the idea of complexity theory oracles. As an added bonus, our multiplexor approximation immediately gives a quantum circuit approximation of diagonal unitary matrices. 1 For an explanation of the notation used in this paper, see Ref.[1] Section 2. Quantum Multiplexors have proved themselves to be very useful as building blocks for quantum computing circuits. For a review of quantum Multiplexors, see Ref.[1] Section 3. As shown in Ref.[2], an Ry(2)-multiplexor with NB controls can be compiled exactly using 2 NB CNOTs. 1 It is believed that this number of CNOTs is a lower bound. It is therefore of interest to find multiplexor approximations with a lower CNOT count. Various multiplexor approximations have been considered before[3]. The goal of this paper is to give a new multiplexor approximation based on the idea of complexity theory oracles. As we shall see, any multiplexor approximation immediately gives an approximation of diagonal unitary matrices. Diagonal unitary matrices of dimension 2 NB can also be compiled exactly using about 2 NB CNOTs[2], and this number is believed to be a lower bound. Consider an arbitrary Ry(2)-multiplexor whose target qubit is labelled τ and whose Nβ control qubits are labelled ⃗ β = (βNβ−1,...,β1, β0). M = exp ⎝i θ ⃗ b σY (τ)P ⃗ b ( ⃗ β
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quantum compiling with approximation of Multiplexors
arXiv: Quantum Physics, 2008Co-Authors: Robert R TucciAbstract:A quantum compiling algorithm is an algorithm for decomposing (“compiling”) an arbitrary unitary matrix into a sequence of elementary operations (SEO). Suppose Uin is an NB-bit unstructured unitary matrix (a unitary matrix with no special symmetries) that we wish to compile. For NB > 10, expressing Uin as a SEO requires more than a million CNOTs. This calls for a method for finding a unitary matrix that: (1)approximates Uin well, and (2 is expressible with fewer CNOTs than Uin. The purpose of this paper is to propose one such approximation method. Various quantum compiling algorithms have been proposed in the literature that decompose Uin into a sequence of U(2)-Multiplexors, each of which is then decomposed into a SEO. Our strategy for approximating Uin is to approximate these intermediate U(2)Multiplexors. In this paper, we will show how one can approximate a U(2)-multiplexor by another U(2)-multiplexor that is expressible with fewer CNOTs.
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Abstract
2008Co-Authors: Robert R TucciAbstract:A quantum compiling algorithm is an algorithm for decomposing (“compiling”) an arbitrary unitary matrix into a sequence of elementary operations (SEO). Suppose Uin is an NB-bit unstructured unitary matrix (a unitary matrix with no special symmetries) that we wish to compile. For NB> 10, expressing Uin as a SEO requires more than a million CNOTs. This calls for a method for finding a unitary matrix that: (1)approximates Uin well, and (2 is expressible with fewer CNOTs than Uin. The purpose of this paper is to propose one such approximation method. Various quantum compiling algorithms have been proposed in the literature that decompose Uin into a sequence of U(2)-Multiplexors, each of which is then decomposed into a SEO. Our strategy for approximating Uin is to approximate these intermediate U(2)Multiplexors. In this paper, we will show how one can approximate a U(2)-multiplexor by another U(2)-multiplexor that is expressible with fewer CNOTs. 1
Makoto Suzuki - One of the best experts on this subject based on the ideXlab platform.
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
IEEE Journal of Solid-state Circuits, 1995Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
Custom Integrated Circuits Conference, 1994Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-/spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77 mm/spl times/3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply. >
Toshiaki Yamanaka - One of the best experts on this subject based on the ideXlab platform.
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
IEEE Journal of Solid-state Circuits, 1995Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >
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a 4 4 ns cmos 54 spl times 54 b multiplier using pass transistor multiplexer
Custom Integrated Circuits Conference, 1994Co-Authors: N Ohkubo, Makoto Suzuki, T Shinbo, Toshiaki Yamanaka, A Shimizu, K Sasaki, Y NakagomeAbstract:A 54/spl times/54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-/spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77 mm/spl times/3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply. >
