The Experts below are selected from a list of 1182 Experts worldwide ranked by ideXlab platform
S.k. Wilson - One of the best experts on this subject based on the ideXlab platform.
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A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis
IEEE Transactions on Signal Processing, 2001Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/Multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the Multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 /spl times/ 16 bit array multiplier implemented in a 0.6-/spl mu/ process with 3.3 V supply voltage.
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ICASSP - High-level modeling of switching activity with application to low-power DSP system synthesis
1999 IEEE International Conference on Acoustics Speech and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258), 1999Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address the issue of high-level synthesis of low-power digital signal processing (DSP) systems by proposing switching activity models. In particular, we present a technology independent hierarchical scheme to compare relative power performance of two competing DSP systems. The basic building blocks considered for such system are a full-adder and a one-bit delay. Estimates of switching activity at the output of these building blocks is used to model the activity in different architectural primitives used for building DSP systems. This method is very fast and simple and simulations show accuracy within 4% of extensive bit-level simulations. Therefore, it can easily be integrated into current communications/DSP CAD tools for low-power applications. The models show that the choice of multiplier/Multiplicand is important when using array multipliers in a data-path. If the input signal with smaller variance is chosen as the as the Multiplicand, up to 20% savings in switching activity can be achieved. This observation is verified by analog simulation.
M. Lundberg - One of the best experts on this subject based on the ideXlab platform.
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A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis
IEEE Transactions on Signal Processing, 2001Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/Multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the Multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 /spl times/ 16 bit array multiplier implemented in a 0.6-/spl mu/ process with 3.3 V supply voltage.
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ICASSP - High-level modeling of switching activity with application to low-power DSP system synthesis
1999 IEEE International Conference on Acoustics Speech and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258), 1999Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address the issue of high-level synthesis of low-power digital signal processing (DSP) systems by proposing switching activity models. In particular, we present a technology independent hierarchical scheme to compare relative power performance of two competing DSP systems. The basic building blocks considered for such system are a full-adder and a one-bit delay. Estimates of switching activity at the output of these building blocks is used to model the activity in different architectural primitives used for building DSP systems. This method is very fast and simple and simulations show accuracy within 4% of extensive bit-level simulations. Therefore, it can easily be integrated into current communications/DSP CAD tools for low-power applications. The models show that the choice of multiplier/Multiplicand is important when using array multipliers in a data-path. If the input signal with smaller variance is chosen as the as the Multiplicand, up to 20% savings in switching activity can be achieved. This observation is verified by analog simulation.
K. Muhammad - One of the best experts on this subject based on the ideXlab platform.
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A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis
IEEE Transactions on Signal Processing, 2001Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/Multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the Multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 /spl times/ 16 bit array multiplier implemented in a 0.6-/spl mu/ process with 3.3 V supply voltage.
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ICASSP - High-level modeling of switching activity with application to low-power DSP system synthesis
1999 IEEE International Conference on Acoustics Speech and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258), 1999Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address the issue of high-level synthesis of low-power digital signal processing (DSP) systems by proposing switching activity models. In particular, we present a technology independent hierarchical scheme to compare relative power performance of two competing DSP systems. The basic building blocks considered for such system are a full-adder and a one-bit delay. Estimates of switching activity at the output of these building blocks is used to model the activity in different architectural primitives used for building DSP systems. This method is very fast and simple and simulations show accuracy within 4% of extensive bit-level simulations. Therefore, it can easily be integrated into current communications/DSP CAD tools for low-power applications. The models show that the choice of multiplier/Multiplicand is important when using array multipliers in a data-path. If the input signal with smaller variance is chosen as the as the Multiplicand, up to 20% savings in switching activity can be achieved. This observation is verified by analog simulation.
K. Roy - One of the best experts on this subject based on the ideXlab platform.
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A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis
IEEE Transactions on Signal Processing, 2001Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/Multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the Multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 /spl times/ 16 bit array multiplier implemented in a 0.6-/spl mu/ process with 3.3 V supply voltage.
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ICASSP - High-level modeling of switching activity with application to low-power DSP system synthesis
1999 IEEE International Conference on Acoustics Speech and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258), 1999Co-Authors: M. Lundberg, K. Muhammad, K. Roy, S.k. WilsonAbstract:We address the issue of high-level synthesis of low-power digital signal processing (DSP) systems by proposing switching activity models. In particular, we present a technology independent hierarchical scheme to compare relative power performance of two competing DSP systems. The basic building blocks considered for such system are a full-adder and a one-bit delay. Estimates of switching activity at the output of these building blocks is used to model the activity in different architectural primitives used for building DSP systems. This method is very fast and simple and simulations show accuracy within 4% of extensive bit-level simulations. Therefore, it can easily be integrated into current communications/DSP CAD tools for low-power applications. The models show that the choice of multiplier/Multiplicand is important when using array multipliers in a data-path. If the input signal with smaller variance is chosen as the as the Multiplicand, up to 20% savings in switching activity can be achieved. This observation is verified by analog simulation.
Wai-sum Chan - One of the best experts on this subject based on the ideXlab platform.
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Actuarial assessment of damages in personal injury litigation: how precise are we?
Law Probability and Risk, 2011Co-Authors: Felix Wai Hon Chan, Wai-sum ChanAbstract:In personal injury litigation, claimants may seek their compensation for future losses or expenses as a lump sum that is determined by the product of a Multiplicand and a multiplier. The Multiplicand represents the annual loss in earnings and other benefits, as assessed at the trial date, while the multiplier discounts future pecuniary values into a single present-day lump sum amount. At present, multipliers in the UK are calculated using actuarial methods and based on assumed mortality and interest rates. However, it is entirely possible that these assumptions are incorrect, and if they are, then all claimants who rely on the same set of actuarial multipliers will be affected. In this article, we investigate how the uncertainty surrounding mortality and interest rate assumptions affects the precision of actuarial multipliers. With the aid of stochastic models, we estimate the possible range of values that an actuarial multiplier can take. Language: en
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Time to Review the Discount Rate in Personal Injury Claims
2010Co-Authors: Wai-sum Chan, Felix Wai Hon ChanAbstract:When assessing future pecuniary loss in personal injury claims, the Multiplicand/multiplier approach is often adopted. An important factor in determining multipliers is the net rate of return (discount rate) the claimant might expect to receive from a reasonably prudent investment of the lump sum compensation.
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Actuarial Assessment of Damages in Personal Injury Litigation in Hong Kong: Chan Pui Ki (an Infant) V. Leung on
The International Journal of Evidence & Proof, 2000Co-Authors: Felix Wai Hon Chan, Wai-sum ChanAbstract:Case note: Actuarial assessment of damages in personal injury litigation in Hong Kong: Chan Pui Ki (an infant) v Leung On. When assessing future pecuniary loss in personal injury litigation, courts often use the Multiplicand/multiplier approach. The objective is to calculate a lump sum amount to compensate the plaintiff for future loss of earnings and to cover a stream of future expenses.
