The Experts below are selected from a list of 24675 Experts worldwide ranked by ideXlab platform
Huazhong Yang - One of the best experts on this subject based on the ideXlab platform.
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on chip sensor network for efficient management of power gating induced power ground noise in Multiprocessor System on chip
IEEE Transactions on Parallel and Distributed Systems, 2013Co-Authors: Weichen Liu, Xuan Wang, Yu Wang, Huazhong YangAbstract:Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on Multiprocessor System on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a Systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total System performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.
Wei Zhang - One of the best experts on this subject based on the ideXlab platform.
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3 d mesh based optical network on chip for Multiprocessor System on chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013Co-Authors: Baihan Huang, Wei Zhang, Zhehui Wang, Xuan Wang, Mahdi Nikdast, Weichen Liu, Zhe WangAbstract:Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to Multiprocessor Systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated technologies offer an opportunity to continue performance improvements with higher integration densities. In this paper, we present a 3-D mesh-based ONoC for MPSoCs, and new low-cost nonblocking 4 × 4, 5 × 5, 6 × 6, and 7 × 7 optical routers for dimension-order routing in the 3-D mesh-based ONoC. Besides, we propose an optimized floorplan for the 3-D mesh-based ONoC. The floorplan follows the regular 3-D mesh topology but implements all optical routers in a single optical layer. The floorplan is optimized to minimize the number of extra waveguide crossings caused when merging the 3-D ONoC to one optical layer. Based on a set of real applications and uniform traffic pattern, we develop a SystemC-based cycle-accurate NoC simulator and compare the 3-D mesh-based ONoC with the matched 2-D mesh-based ONoC and 2-D electronic NoC for performance and energy efficiency. Additionally, we quantitatively analyze thermal effects on the 3-D 8 × 8 × 2 mesh-based ONoC.
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a torus based hierarchical optical electronic network on chip for Multiprocessor System on chip
ACM Journal on Emerging Technologies in Computing Systems, 2012Co-Authors: Wei Zhang, Weichen Liu, Mahdi NikdastAbstract:Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for Multiprocessor Systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84p less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99p of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75p of laser sources and half of optical receivers compared with the optical torus-based NoC.
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A low-power fat tree-based optical Network-On-Chip for Multiprocessor System-on-chip
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., 2009Co-Authors: Huaxi Gu, Jiang Xu, Wei ZhangAbstract:Multiprocessor System-on-chip (MPSoC) is an attractive platform for high-performance applications. Networks-on-chip (NoCs) can improve the on-chip communication bandwidth of MPSoCs. However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and microresonators, and promise significant bandwidth and power advantages. This paper proposes a fat tree-based optical NoC (FONoC) including its topology, floorplan, protocols, and a low-power and low-cost optical router, optical turnaround router (OTAR). Different from other optical NoCs, FONoC does not require building a separate electronic NoC for network control. It carries both payload data and network control data on the same optical network, while using circuit switching for the former and packet switching for the latter. The FONoC protocols are designed to minimize network control data and the related power consumption. An optimized turnaround routing algorithm is designed to utilize the low-power feature of OTAR, which can passively route packets without powering on any microresonator in 40% of all cases. Comparing with other optical routers, OTAR has the lowest optical power loss and uses the lowest number of microresonators. An analytical model is developed to characterize the power consumption of FONoC. We compare the power consumption of FONoC with a matched electronic NoC in 45 nm, and show that FONoC can save 87% power comparing with the electronic NoC on a 64-core MPSoC. We simulate the FONoC for the 64-core MPSoC and show the end-to-end delay and network throughput under different offered loads and packet sizes.
Wayne Wolf - One of the best experts on this subject based on the ideXlab platform.
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Multiprocessor System on chip mpsoc technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: Wayne Wolf, A A Jerraya, G MartinAbstract:The Multiprocessor System-on-chip (MPSoC) uses multiple CPUs along with other hardware subSystems to implement a System. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.
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the future of Multiprocessor Systems on chips
Design Automation Conference, 2004Co-Authors: Wayne WolfAbstract:This paper surveys the state-of-the-art and pending challenges in MPSoC design. Standards in communications, multimedia, networking, and other areas encourage the development of high-performance platforms that can support a range of implementations of the standard. A Multiprocessor System-on-chip includes embedded processors, digital logic, and mixed-signal circuits combined into a heterogeneous Multiprocessor. This mix of technologies creates a major challenge for MPSoC design teams. We will look at some existing MPSoC designs and then describe some hardware and software challenges for MPSoC designers.
Weichen Liu - One of the best experts on this subject based on the ideXlab platform.
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3 d mesh based optical network on chip for Multiprocessor System on chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013Co-Authors: Baihan Huang, Wei Zhang, Zhehui Wang, Xuan Wang, Mahdi Nikdast, Weichen Liu, Zhe WangAbstract:Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to Multiprocessor Systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated technologies offer an opportunity to continue performance improvements with higher integration densities. In this paper, we present a 3-D mesh-based ONoC for MPSoCs, and new low-cost nonblocking 4 × 4, 5 × 5, 6 × 6, and 7 × 7 optical routers for dimension-order routing in the 3-D mesh-based ONoC. Besides, we propose an optimized floorplan for the 3-D mesh-based ONoC. The floorplan follows the regular 3-D mesh topology but implements all optical routers in a single optical layer. The floorplan is optimized to minimize the number of extra waveguide crossings caused when merging the 3-D ONoC to one optical layer. Based on a set of real applications and uniform traffic pattern, we develop a SystemC-based cycle-accurate NoC simulator and compare the 3-D mesh-based ONoC with the matched 2-D mesh-based ONoC and 2-D electronic NoC for performance and energy efficiency. Additionally, we quantitatively analyze thermal effects on the 3-D 8 × 8 × 2 mesh-based ONoC.
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on chip sensor network for efficient management of power gating induced power ground noise in Multiprocessor System on chip
IEEE Transactions on Parallel and Distributed Systems, 2013Co-Authors: Weichen Liu, Xuan Wang, Yu Wang, Huazhong YangAbstract:Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on Multiprocessor System on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a Systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total System performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.
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a torus based hierarchical optical electronic network on chip for Multiprocessor System on chip
ACM Journal on Emerging Technologies in Computing Systems, 2012Co-Authors: Wei Zhang, Weichen Liu, Mahdi NikdastAbstract:Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for Multiprocessor Systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84p less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99p of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75p of laser sources and half of optical receivers compared with the optical torus-based NoC.
A A Jerraya - One of the best experts on this subject based on the ideXlab platform.
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Multiprocessor System on chip mpsoc technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: Wayne Wolf, A A Jerraya, G MartinAbstract:The Multiprocessor System-on-chip (MPSoC) uses multiple CPUs along with other hardware subSystems to implement a System. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.
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hardware software codesign of on chip communication architecture for application specific Multiprocessor System on chip
International Journal of Embedded Systems, 2005Co-Authors: Nacereddine Zergainoh, Amer Baghdadi, A A JerrayaAbstract:System-on-chip (SoC) is developing as a new paradigm in electronic System design. This allows an entire hardware/software System to be built on a single chip, using predesigned components. This paper examines the achievements and future of novel approach and flow for an efficient design of application-specific Multiprocessor System-on-chip (called GAM-SoC). The approach is based on a generic architecture model, which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability, which make it reusable for a large class of applications. In the flow, architectural parameters are first extracted from a high-level System specification and then used to instantiate architectural components, such as processors, memory modules, IP-hardware blocks and on-chip communication networks. The flow includes the generation of hardware/software wrappers that adapts the processor to the on-chip communication network in an application-specific way. The feasibility and effectiveness of this approach are illustrated by significant demonstration examples.
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automatic generation of application specific architectures for heterogeneous Multiprocessor System on chip
Design Automation Conference, 2001Co-Authors: D Lyonnard, Sungjoo Yoo, Amer Baghdadi, A A JerrayaAbstract:We present a design flow for the generation of application-specific Multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level System specification. Parameters are used to instantiate architectural components, such as processors, memory modules and communication networks. The flow includes the automatic generation of a communication coprocessor that adapts the processor to the communication network in an application-specific way. Experiments with two System examples show the effectiveness of the presented design flow.
