The Experts below are selected from a list of 273 Experts worldwide ranked by ideXlab platform
Sanjay Jinturkar - One of the best experts on this subject based on the ideXlab platform.
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A low-power Multithreaded Processor for software defined radio
Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2006Co-Authors: Michael Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Sanjay Jinturkar, Stamatis VassiliadisAbstract:Embedded digital signal Processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these Processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power Multithreaded digital signal Processor for software defined radio. The Processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the Processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the Processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the Processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.
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Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Daniela Iancu, Michael J. Schulte, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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CASES - Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Michael J. Schulte, Daniel Iancu, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
Suman Mamidi - One of the best experts on this subject based on the ideXlab platform.
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A low-power Multithreaded Processor for software defined radio
Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2006Co-Authors: Michael Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Sanjay Jinturkar, Stamatis VassiliadisAbstract:Embedded digital signal Processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these Processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power Multithreaded digital signal Processor for software defined radio. The Processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the Processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the Processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the Processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.
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Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Daniela Iancu, Michael J. Schulte, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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CASES - Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Michael J. Schulte, Daniel Iancu, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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a low power Multithreaded Processor for baseband communication systems
International Conference Workshop on Embedded Computer Systems: Architectures Modeling and Simulation, 2004Co-Authors: Michael J. Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Stamatis VassiliadisAbstract:Embedded digital signal Processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, these Processors should be compiler-friendly, so that code for them can quickly be developed in a high-level language. This paper presents the design of a high-performance, low-power digital signal Processor for baseband communication systems. The Processor uses token triggered threading, SIMD vector processing, and powerful compound instructions to provide real-time baseband processing capabilities with very low power consumption. Using a super-computer class vectorizing compiler, the Processor achieves real-time performance on a 2Mbps WCDMA transmission system.
Dean M. Tullsen - One of the best experts on this subject based on the ideXlab platform.
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Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices
IEEE Transactions on Parallel and Distributed Systems, 2008Co-Authors: Carlos Madriles, Dean M. Tullsen, Carlos García-quiñones, Pedro Marcuello, Antonio Gonzalez, Jesus Sanchez, Hong Wang, John P. ShenAbstract:This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism speculatively, that is, executing code in parallel, even when the compiler or runtime system cannot guarantee that the parallelism exists. The proposed approach is based on predicting/computing thread input values via software through a piece of code that is added at the beginning of each thread (the precomputation slice). A precomputation slice is expected to compute the correct thread input values most of the time but not necessarily always. This allows aggressive optimization techniques to be applied to the slice to make it very short. This paper focuses on the microarchitecture that supports this execution model. The primary novelty of the microarchitecture is the hardware support for the execution and validation of precomputation slices. Additionally, this paper presents new architectures for the register file and the cache memory in order to support multiple versions of each variable and allow for efficient rollback in case of misspeculation. We show that the proposed microarchitecture, together with the compiler support, achieves an average speedup of 2.2 for applications that conventional nonspeculative approaches are not able to parallelize at all.
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symbiotic jobscheduling for a simultaneous Multithreaded Processor
Architectural Support for Programming Languages and Operating Systems, 2000Co-Authors: Allan Snavely, Dean M. TullsenAbstract:Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coscheduleThis paper demonstrates that performance on a hardware Multithreaded Processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without any advance knowledge of a workload's characteristics, using sampling to identify jobs which run well together.We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about various possible schedules, and a symbiosis phase which uses that information to predict which schedule will provide the best performance. We show that a small sample of the possible schedules is sufficient to identify a good schedule quickly. On a system with random job arrivals and departures, response time is improved as much as 17% over a schedule which does not incorporate symbiosis.
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ASPLOS - Symbiotic jobscheduling for a simultaneous Multithreaded Processor
ACM SIGPLAN Notices, 2000Co-Authors: Allan Snavely, Dean M. TullsenAbstract:Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coscheduleThis paper demonstrates that performance on a hardware Multithreaded Processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without any advance knowledge of a workload's characteristics, using sampling to identify jobs which run well together.We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about various possible schedules, and a symbiosis phase which uses that information to predict which schedule will provide the best performance. We show that a small sample of the possible schedules is sufficient to identify a good schedule quickly. On a system with random job arrivals and departures, response time is improved as much as 17% over a schedule which does not incorporate symbiosis.
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HPCA - Supporting fine-grained synchronization on a simultaneous multithreading Processor
Proceedings Fifth International Symposium on High-Performance Computer Architecture, 1999Co-Authors: Dean M. Tullsen, Susan J. Eggers, H.m. LevyAbstract:This paper proposes and evaluates new synchronization schemes for a simultaneous Multithreaded Processor. We present a scalable mechanism that permits threads to cheaply synchronize within the Processor, with blocked threads consuming no Processor resources. We also introduce the concept of lock release prediction, which gains an additional improvement of 40%. Overall, we show that these improvements in synchronization cost enable parallelization of code that could not be effectively parallelized using traditional techniques.
John Glossner - One of the best experts on this subject based on the ideXlab platform.
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A low-power Multithreaded Processor for software defined radio
Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2006Co-Authors: Michael Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Sanjay Jinturkar, Stamatis VassiliadisAbstract:Embedded digital signal Processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these Processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power Multithreaded digital signal Processor for software defined radio. The Processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the Processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the Processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the Processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.
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Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Daniela Iancu, Michael J. Schulte, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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CASES - Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Michael J. Schulte, Daniel Iancu, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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a low power Multithreaded Processor for baseband communication systems
International Conference Workshop on Embedded Computer Systems: Architectures Modeling and Simulation, 2004Co-Authors: Michael J. Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Stamatis VassiliadisAbstract:Embedded digital signal Processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, these Processors should be compiler-friendly, so that code for them can quickly be developed in a high-level language. This paper presents the design of a high-performance, low-power digital signal Processor for baseband communication systems. The Processor uses token triggered threading, SIMD vector processing, and powerful compound instructions to provide real-time baseband processing capabilities with very low power consumption. Using a super-computer class vectorizing compiler, the Processor achieves real-time performance on a 2Mbps WCDMA transmission system.
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a Multithreaded Processor architecture for sdr
한국통신학회지(정보와통신), 2002Co-Authors: John Glossner, Tanuj Raja, Erdem Hokenek, Mayan MoudgillAbstract:In this paper we discuss a Multithreaded baseband Processor capable of executing all physical layer processing of high data rate communications systems completely in software. We discuss the enabling technology for a software defined radio approach and present results for GPRS, 802.11b, and 2Mbps WCDMA. All of these protocols can be executed in real-time on the SB9600 chip using the Sandblaster core.
Mayan Moudgill - One of the best experts on this subject based on the ideXlab platform.
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A low-power Multithreaded Processor for software defined radio
Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2006Co-Authors: Michael Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Sanjay Jinturkar, Stamatis VassiliadisAbstract:Embedded digital signal Processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these Processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power Multithreaded digital signal Processor for software defined radio. The Processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the Processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the Processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the Processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.
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Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Daniela Iancu, Michael J. Schulte, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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CASES - Instruction set extensions for software defined radio on a Multithreaded Processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Michael J. Schulte, Daniel Iancu, Sanjay JinturkarAbstract:Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power Multithreaded Processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
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a low power Multithreaded Processor for baseband communication systems
International Conference Workshop on Embedded Computer Systems: Architectures Modeling and Simulation, 2004Co-Authors: Michael J. Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Stamatis VassiliadisAbstract:Embedded digital signal Processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, these Processors should be compiler-friendly, so that code for them can quickly be developed in a high-level language. This paper presents the design of a high-performance, low-power digital signal Processor for baseband communication systems. The Processor uses token triggered threading, SIMD vector processing, and powerful compound instructions to provide real-time baseband processing capabilities with very low power consumption. Using a super-computer class vectorizing compiler, the Processor achieves real-time performance on a 2Mbps WCDMA transmission system.
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a Multithreaded Processor architecture for sdr
한국통신학회지(정보와통신), 2002Co-Authors: John Glossner, Tanuj Raja, Erdem Hokenek, Mayan MoudgillAbstract:In this paper we discuss a Multithreaded baseband Processor capable of executing all physical layer processing of high data rate communications systems completely in software. We discuss the enabling technology for a software defined radio approach and present results for GPRS, 802.11b, and 2Mbps WCDMA. All of these protocols can be executed in real-time on the SB9600 chip using the Sandblaster core.
