The Experts below are selected from a list of 7581 Experts worldwide ranked by ideXlab platform

P Verma - One of the best experts on this subject based on the ideXlab platform.

  • assessing software reliability performance under highly critical but infrequent event occurrences
    International Symposium on Software Reliability Engineering, 1997
    Co-Authors: M S Alam, W H Chen, W K Ehrlich, M E Engel, D A Kropfl, P Verma
    Abstract:

    Operational testing is expensive and time-consuming in applications with highly critical but infrequent event occurrences, and procedures are needed for obtaining valid software reliability estimates. Two such procedures are accelerated stress testing and experimental design techniques. Examples of accelerated stress in software include: a higher request arrival rate, increasing data traffic "burstiness", and so on. Furthermore, when the software is tested by executing the system under emergency conditions or exception events, it is critical that experimental design techniques are used to account for "carry-over" effects in failure performance. An application of software reliability testing of a telecommunication system Node Controller is used to describe the issues and our overall approach to software reliability assessment. The reliability projections based on our approach are compared to reliability estimates derived analytically and through simulation. Our results suggest that these statistical techniques are useful techniques for measuring reliability performance under critical events that have a low probability of occurrence.

  • ISSRE - Assessing software reliability performance under highly critical but infrequent event occurrences
    Proceedings The Eighth International Symposium on Software Reliability Engineering, 1
    Co-Authors: M S Alam, W H Chen, W K Ehrlich, M E Engel, D A Kropfl, P Verma
    Abstract:

    Operational testing is expensive and time-consuming in applications with highly critical but infrequent event occurrences, and procedures are needed for obtaining valid software reliability estimates. Two such procedures are accelerated stress testing and experimental design techniques. Examples of accelerated stress in software include: a higher request arrival rate, increasing data traffic "burstiness", and so on. Furthermore, when the software is tested by executing the system under emergency conditions or exception events, it is critical that experimental design techniques are used to account for "carry-over" effects in failure performance. An application of software reliability testing of a telecommunication system Node Controller is used to describe the issues and our overall approach to software reliability assessment. The reliability projections based on our approach are compared to reliability estimates derived analytically and through simulation. Our results suggest that these statistical techniques are useful techniques for measuring reliability performance under critical events that have a low probability of occurrence.

Qing-hai Zhang - One of the best experts on this subject based on the ideXlab platform.

Claudio Sansoe - One of the best experts on this subject based on the ideXlab platform.

  • FPL - An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
    Lecture Notes in Computer Science, 2002
    Co-Authors: Roberto Gaudino, Vito De Feo, Marcello Chiaberge, Claudio Sansoe
    Abstract:

    We present architecture and experimental results for an highspeed digital Node Controller developed in the "RINGO" project, a demonstrator of a next-generation ultra-high capacityn etwork based on WDM optical fiber ring. The MAC protocol and other Controller functions have been developed on a high capacityF PGA, which supports efficient input queuing and multicast capabilities byh andling several concurrent real time processes.

Ninghui Sun - One of the best experts on this subject based on the ideXlab platform.

  • PDCAT - cHPP Controller: A High Performance Hyper-Node Hardware Accelerator
    2013 International Conference on Parallel and Distributed Computing Applications and Technologies, 2013
    Co-Authors: Feilong Liu, Zheng Cao, Zhan Wang, Xiaoli Liu, Ninghui Sun
    Abstract:

    The high-density blade server provides an attractive solution for the rapid increasing demand on computing. The degree of parallelism inside a blade enclosure nowadays has reach up to hundreds of cores. In such parallelism, it is necessary to accelerate communications inside a blade enclosure. However, commercial products seldom set foot in the optimization based on hardware. A hyper-Node Controller is proposed to provide a low overhead and high performance interconnection based on PCIe, which supports global address space, user-level communication, and efficient communication primitives. Furthermore, the efficient sharing of I/O resource is another goal of this design. The prototype of the hyper-Node Controller is implemented in FPGA. The testing results show the lowest latency is only 1.242us and the highest bandwidth is 3.19GB/s, which is almost 99.7% of the theoretic peak bandwidth.

  • HPCC - Adding an Expressway to Accelerate the Neighborhood Communication
    2010 IEEE 12th International Conference on High Performance Computing and Communications (HPCC), 2010
    Co-Authors: Kai Wang, Fei Chen, Zheng Cao, Ninghui Sun
    Abstract:

    The blade system is very popular in high performance computing. In a blade system, the blade is a fundamental element in which are symmetric multi-processors (SMP). About ten blades constitute a blade box, several blade boxes constitute a cabinet and some cabinets constitute a blade system at last. The blades in a blade box are neighbors because they have relatively short distance. Programmers always try to place the tightly related processes into the same blade box. However, there’s seldom any optimization made by hardware to accelerate the communication in a blade box. Thus, a single chip design called hyper-Node Controller is presented to provide ultra low latency and high bandwidth which resembles an expressway between neighbors. All the Nodes in a blade box can act as a single hyper Node by using the hyper-Node Controller. It is apparent that the additional Controller is a useful supplement to efficiently enhance the communication in a blade box and finally enhance the entire blade system. A FPGA prototype of the hyper-Node Controller has been implemented and it can connect five blades simultaneously. In the preliminary performance evaluation, the latency for an 8-byte payload between two blades is less than 1us, 1.33GB/s which is nearly 94% of the peak effective bandwidth can be obtained by transferring messages with a payload of only 256 bytes.

  • hpp Controller an intra Node Controller designed for connecting heterogeneous cpus
    International Conference on Cluster Computing, 2009
    Co-Authors: Panyong Zhang, Ninghui Sun
    Abstract:

    Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one Node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial Results show that HPP-Controller has low latency of 0.75us and high bandwidth close to bandwith of HT links.

  • CLUSTER - HPP-Controller: An intra-Node Controller designed for connecting heterogeneous CPUs
    2009 IEEE International Conference on Cluster Computing and Workshops, 2009
    Co-Authors: Panyong Zhang, Ninghui Sun
    Abstract:

    Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one Node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial Results show that HPP-Controller has low latency of 0.75us and high bandwidth close to bandwith of HT links.

Roberto Gaudino - One of the best experts on this subject based on the ideXlab platform.

  • ONDM - RingO: a demonstrator of WDM optical packet network on a ring topology
    Next Generation Optical Network Design and Modelling, 2003
    Co-Authors: Andrea Carena, Roberto Gaudino, Vito De Feo, Valter Ferrero, Fabio Neri, Pierluigi Poggiolini
    Abstract:

    This paper presents the work carried out by the Optical Communication Group at Politecnico di Torino in the framework of the RINGO project. The RINGO network is based on a WDM optical ring, with an input queuing access protocol and multicast capabilities. In this paper we present the network architecture and Node structure, together with the results obtained on the RINGO experimental demonstrator. We investigate several important transmission issues, such as EDFA gain locking, and the implementation of several subsystems, such as Node Controller, λ-monitor and packet transmitter.

  • FPL - An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
    Lecture Notes in Computer Science, 2002
    Co-Authors: Roberto Gaudino, Vito De Feo, Marcello Chiaberge, Claudio Sansoe
    Abstract:

    We present architecture and experimental results for an highspeed digital Node Controller developed in the "RINGO" project, a demonstrator of a next-generation ultra-high capacityn etwork based on WDM optical fiber ring. The MAC protocol and other Controller functions have been developed on a high capacityF PGA, which supports efficient input queuing and multicast capabilities byh andling several concurrent real time processes.