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Michiel Steyaert - One of the best experts on this subject based on the ideXlab platform.

  • a fully integrated cmos dcs 1800 frequency synthesizer
    International Solid-State Circuits Conference, 1998
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-Noise Voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 /spl mu/s, and the phase Noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset.

  • a 1 8 ghz low phase Noise cmos vco using optimized hollow spiral inductors
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    A completely integrated 1.8-GHz low-phase-Noise Voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase Noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range.

  • rf integrated circuits in standard cmos technologies
    European Solid-State Circuits Conference, 1996
    Co-Authors: Michiel Steyaert, Jan Craninckx, M Borremans, Jan Crols, Johan Janssens, Peter R Kinget
    Abstract:

    Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep sub-micron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research groups have developed high performance down-converters, low phase Noise Voltage controlled oscillators and dual modulus prescalers in standard CMOS technologies. The research has already demonstrated fully integrated receivers and VCO circuits with no external components, nor tuning or trimming. Further research on low Noise amplifiers, up-converters, synthesizers and power amplifiers will hopefully result in CMOS RF circuits for fully integrated transceivers for telecommunication applications.

  • a 1 8 ghz cmos low phase Noise Voltage controlled oscillator with prescaler
    IEEE Journal of Solid-state Circuits, 1995
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    The implementation of the two high-frequency building blocks for a low-phase-Noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-/spl mu/m CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low Noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase Noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between Noise and power. The realized VCO has a phase Noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW.

  • low Noise Voltage controlled oscillators using enhanced lc tanks
    IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 1995
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    Frequency synthesizers used in modern telecommunication systems, such as cellular telephones, need to have very low phase Noise. Therefore, in the design of high performance frequency synthesizers using Phase Locked Loops (PLL), the Voltage-Controlled Oscillator (VCO) has become a key issue. The trend towards monolithic Integration poses some major challenges. This paper discusses the phase Noise aspects of LC-tuned oscillators. A general formula is developed, based on the concepts of effective resistance and capacitance. The formula also applies for oscillators using active inductors. From these results the importance of an inductor with very low series resistance is apparent. To circumvent the technological limits given by an Inductor's series resistance, a presented enhanced LC-tank can be used to make a trade-off between Noise and power.

Jan Craninckx - One of the best experts on this subject based on the ideXlab platform.

  • a fully integrated cmos dcs 1800 frequency synthesizer
    International Solid-State Circuits Conference, 1998
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-Noise Voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 /spl mu/s, and the phase Noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset.

  • a 1 8 ghz low phase Noise cmos vco using optimized hollow spiral inductors
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    A completely integrated 1.8-GHz low-phase-Noise Voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase Noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range.

  • rf integrated circuits in standard cmos technologies
    European Solid-State Circuits Conference, 1996
    Co-Authors: Michiel Steyaert, Jan Craninckx, M Borremans, Jan Crols, Johan Janssens, Peter R Kinget
    Abstract:

    Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep sub-micron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research groups have developed high performance down-converters, low phase Noise Voltage controlled oscillators and dual modulus prescalers in standard CMOS technologies. The research has already demonstrated fully integrated receivers and VCO circuits with no external components, nor tuning or trimming. Further research on low Noise amplifiers, up-converters, synthesizers and power amplifiers will hopefully result in CMOS RF circuits for fully integrated transceivers for telecommunication applications.

  • a 1 8 ghz cmos low phase Noise Voltage controlled oscillator with prescaler
    IEEE Journal of Solid-state Circuits, 1995
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    The implementation of the two high-frequency building blocks for a low-phase-Noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-/spl mu/m CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low Noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase Noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between Noise and power. The realized VCO has a phase Noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW.

  • low Noise Voltage controlled oscillators using enhanced lc tanks
    IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 1995
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    Frequency synthesizers used in modern telecommunication systems, such as cellular telephones, need to have very low phase Noise. Therefore, in the design of high performance frequency synthesizers using Phase Locked Loops (PLL), the Voltage-Controlled Oscillator (VCO) has become a key issue. The trend towards monolithic Integration poses some major challenges. This paper discusses the phase Noise aspects of LC-tuned oscillators. A general formula is developed, based on the concepts of effective resistance and capacitance. The formula also applies for oscillators using active inductors. From these results the importance of an inductor with very low series resistance is apparent. To circumvent the technological limits given by an Inductor's series resistance, a presented enhanced LC-tank can be used to make a trade-off between Noise and power.

Felix A. Levinzon - One of the best experts on this subject based on the ideXlab platform.

  • Ultra-low-Noise high-input impedance amplifier for low-frequency measurement applications
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2008
    Co-Authors: Felix A. Levinzon
    Abstract:

    The design of a low-frequency high-input-impedance amplifier having probably the lowest Noise ever reported is presented. The amplifier's frequency range is from about 0.07 Hz to about 110 kHz at the -3-dB level. The equivalent input Noise Voltage spectral density is about 5.6, 1.4, 0.6, and 0.5 nV/radicHz at frequencies 0.1, 1, 10, and 1000 Hz, respectively. Gain of the amplifier is about 83 dB. Noise analysis is made for active-type, capacitive-type, and low impedance signal sources. The contribution from different Noise sources in the amplifier and JFET to the overall Noise is shown.

Y Jin - One of the best experts on this subject based on the ideXlab platform.

  • ultra low Noise hemts for high impedance and low frequency preamplifiers realization and characterization from 4 2 k to 77 k
    Journal of Physics: Conference Series, 2014
    Co-Authors: Y Jin, Q Dong, Y X Liang, A Cavanna, U Gennser, L Couraud, C Ulysse
    Abstract:

    We report on the experimental results of specially designed HEMTs made at CNRS/LPN. These HEMT s, with a resistance input and different capacitance inputs, have been characterized from 4.2 K to 77 K with a power consumption of 100 μW. At 4.2 K, the lowest input Noise Voltage, 6 nV/Hz1/2 at 1 Hz, has been obtained with the HEMT having the largest input capacitance; the lowest input Noise current of about 3 aA/Hz1/2 at 1 Hz has been observed with the HEMT with the smallest input capacitance; and the white Noise Voltage in these HEMTs is of about 0.2 nV/Hz1/2. By increasing the temperature from 4.2 K to 77 K, Noise Voltage and Noise current increase, but their values are limited within a factor of about 3 compared with their lowest values at 4.2 K. Our results show that the HEMT can be a promising transistor to fill the gap for FETs below 100 K for high-impedance and low- frequency readout electronics.

  • ultra low Noise hemts for deep cryogenic low frequency and high impedance readout electronics
    IEEE International Conference on Solid-State and Integrated Circuit Technology, 2014
    Co-Authors: Y Jin, Q Dong, A Cavanna, U Gennser, L Couraud, C Ulysse
    Abstract:

    In order to fill the gap of low-temperature and low-frequency Noise field-effect transistors and to meet the needs in various experiments under deep cryogenic conditions, specially designed HEMTs with different gate capacitances have been fabricated and characterized at 4.2 and 77 K. At 4.2 K and with an appropriate gate capacitances, the obtained lowest input Noise Voltage at 1 Hz is 6 nV/Hz1/2; the lowest input Noise current at 1 Hz is about 3 aA/Hz1/2; their white Noise Voltage is about 0.2 nV/Hz1/2; and for switch applications, the channel resistance can be varied from about 10 Ω to more than 10 GO with a gate leakage current lower than 1 pA.

  • ultra low Noise high electron mobility transistors for high impedance and low frequency deep cryogenic readout electronics
    Applied Physics Letters, 2014
    Co-Authors: Q Dong, Y X Liang, A Cavanna, U Gennser, L Couraud, D Ferry, Y Jin
    Abstract:

    We report on the results obtained from specially designed high electron mobility transistors at 4.2 K: the gate leakage current can be limited lower than 1 aA, and the equivalent input Noise-Voltage and Noise-current at 1 Hz can reach 6.3 nV/Hz1∕2 and 20 aA/Hz1∕2, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.

Q Dong - One of the best experts on this subject based on the ideXlab platform.

  • ultra low Noise hemts for high impedance and low frequency preamplifiers realization and characterization from 4 2 k to 77 k
    Journal of Physics: Conference Series, 2014
    Co-Authors: Y Jin, Q Dong, Y X Liang, A Cavanna, U Gennser, L Couraud, C Ulysse
    Abstract:

    We report on the experimental results of specially designed HEMTs made at CNRS/LPN. These HEMT s, with a resistance input and different capacitance inputs, have been characterized from 4.2 K to 77 K with a power consumption of 100 μW. At 4.2 K, the lowest input Noise Voltage, 6 nV/Hz1/2 at 1 Hz, has been obtained with the HEMT having the largest input capacitance; the lowest input Noise current of about 3 aA/Hz1/2 at 1 Hz has been observed with the HEMT with the smallest input capacitance; and the white Noise Voltage in these HEMTs is of about 0.2 nV/Hz1/2. By increasing the temperature from 4.2 K to 77 K, Noise Voltage and Noise current increase, but their values are limited within a factor of about 3 compared with their lowest values at 4.2 K. Our results show that the HEMT can be a promising transistor to fill the gap for FETs below 100 K for high-impedance and low- frequency readout electronics.

  • ultra low Noise hemts for deep cryogenic low frequency and high impedance readout electronics
    IEEE International Conference on Solid-State and Integrated Circuit Technology, 2014
    Co-Authors: Y Jin, Q Dong, A Cavanna, U Gennser, L Couraud, C Ulysse
    Abstract:

    In order to fill the gap of low-temperature and low-frequency Noise field-effect transistors and to meet the needs in various experiments under deep cryogenic conditions, specially designed HEMTs with different gate capacitances have been fabricated and characterized at 4.2 and 77 K. At 4.2 K and with an appropriate gate capacitances, the obtained lowest input Noise Voltage at 1 Hz is 6 nV/Hz1/2; the lowest input Noise current at 1 Hz is about 3 aA/Hz1/2; their white Noise Voltage is about 0.2 nV/Hz1/2; and for switch applications, the channel resistance can be varied from about 10 Ω to more than 10 GO with a gate leakage current lower than 1 pA.

  • Ultra-low Noise hemts for high-impedance and low-frequency preamplifiers: Realization and characterization from 4.2 k to 77 k
    2014 11th International Workshop on Low Temperature Electronics (WOLTE), 2014
    Co-Authors: Q Dong, Y X Liang, A Cavanna, U Gennser, L Couraud, C Ulysse
    Abstract:

    Si JFETs have been for decades the lowest Noise field-effect transistor (FET) for high-impedance and low-frequency readout electronics. However, they are based on nondegenerate carriers, and their operating temperature is limited to higher than 100 K due to freeze-out of carriers. Being based on degenerate carriers, the HEMT has no low-temperature limit. Here, we report on the experimental results of specially designed HEMTs made at CNRS/LPN. These HEMTs, with different input capacitances from 92 pF to 5.3 pF, have been characterized from 4.2 K to 77 K, and show a power consumption of 100 μW or below. At 4.2 K, the lowest input Noise Voltage, 6 nV/Hz1/2 at 1 Hz, has been obtained with the HEMT having the largest input capacitance; the lowest input Noise current of about 3 aA/Hz1/2 at 1 Hz has been observed with the HEMT with the smallest input capacitance; and the white Noise Voltage in these HEMTs is of about 0.2 nV/Hz1/2. By increasing the temperature from 4.2 K to 77 K, Noise Voltage and Noise current increase, but their values are limited within a factor of about 3 compared to their lowest values at 4.2 K. Our results show that the HEMT can be a promising transistor to fill the gap for FETs below 100 K for high-impedance and low-frequency readout electronics.

  • ultra low Noise high electron mobility transistors for high impedance and low frequency deep cryogenic readout electronics
    Applied Physics Letters, 2014
    Co-Authors: Q Dong, Y X Liang, A Cavanna, U Gennser, L Couraud, D Ferry, Y Jin
    Abstract:

    We report on the results obtained from specially designed high electron mobility transistors at 4.2 K: the gate leakage current can be limited lower than 1 aA, and the equivalent input Noise-Voltage and Noise-current at 1 Hz can reach 6.3 nV/Hz1∕2 and 20 aA/Hz1∕2, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.