The Experts below are selected from a list of 19860 Experts worldwide ranked by ideXlab platform
Venkatesh Akella - One of the best experts on this subject based on the ideXlab platform.
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Segmented bitline cache : Exploiting non-uniform memory access patterns
Lecture Notes in Computer Science, 2006Co-Authors: Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh AkellaAbstract:On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the overall bitline capacitance. The success of this cache relies on accessing segments near the sense-amps much more often than remote segments. We show that the access pattern to the first level data and instruction cache is extremely skewed. Only a small set of cache lines are accessed frequently. We exploit this non-uniform cache access pattern by mapping the frequently accessed cache lines closer to the sense amp. These lines are isolated by segmenting circuits on the bitlines and hence dissipate lesser power when accessed. Modifications to the address decoder enable a dynamic re-mapping of cache lines to segments. In this paper, we explore the design-space of segmenting the level one data and instruction caches. Instruction and data caches show potential power savings of 10% and 6% respectively on the subset of benchmarks simulated.
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HiPC - Segmented bitline cache: exploiting non-uniform memory access patterns
High Performance Computing - HiPC 2006, 2006Co-Authors: Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh AkellaAbstract:On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the overall bitline capacitance. The success of this cache relies on accessing segments near the sense-amps much more often than remote segments. We show that the access pattern to the first level data and instruction cache is extremely skewed. Only a small set of cache lines are accessed frequently. We exploit this non-uniform cache access pattern by mapping the frequently accessed cache lines closer to the sense amp. These lines are isolated by segmenting circuits on the bitlines and hence dissipate lesser power when accessed. Modifications to the address decoder enable a dynamic re-mapping of cache lines to segments. In this paper, we explore the design-space of segmenting the level one data and instruction caches. Instruction and data caches show potential power savings of 10% and 6% respectively on the subset of benchmarks simulated.
Alistair P. Rendell - One of the best experts on this subject based on the ideXlab platform.
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ISPAN - Effective Use of Dynamic Page Migration on NUMA Platforms: The Gaussian Chemistry Code on the SunFire X4600M2 System
2009 10th International Symposium on Pervasive Systems Algorithms and Networks, 2009Co-Authors: Rui Yang, Joseph Antony, Alistair P. RendellAbstract:In this work we study the effect of data locality on the performance of Gaussian 03 code running on a multi-core non-uniform memory access (NUMA) system. A user-space protocol which affects runtime data locality, through the use of dynamic page migration and interleaving techniques, is considered. Using this protocol results in a significant performance improvement. Results for parallel Gaussian 03 using up to 16 threads are presented. The overhead of page migration and effect of dual-core contention are also examined.
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HPCC - A Simple Performance Model for Multithreaded Applications Executing on non-uniform memory access Computers
2009 11th IEEE International Conference on High Performance Computing and Communications, 2009Co-Authors: Rui Yang, Joseph Antony, Alistair P. RendellAbstract:In this work, we extend and evaluate a simple performance model to account for NUMA and bandwidth effects for single and multi-threaded calculations within the Gaussian 03 computational chemistry code on a contemporary multi-core, NUMA platform. By using the thread and memory placement APIs in Solaris, we present results for a set of calculations from which we analyze on-chip interconnect and intra-core bandwidth contention and show the importance of load-balancing between threads. The extended model predicts single threaded performance to within 1% errors and most multi-threaded experiments within 15% errors. Our results and modeling shows that accounting for bandwidth constraints within user-space code is beneficial.
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International Conference on Computational Science - OpenMP and NUMA architectures I: Investigating memory placement on the SGI origin 3000
Lecture Notes in Computer Science, 2003Co-Authors: Nathan Robertson, Alistair P. RendellAbstract:The OpenMP programming model is based upon the assumption of uniform memory access. Virtually all current day large scale shared memory computers exhibit some degree of non-uniform memory access (NUMA). Should OpenMP be extended for NUMA architectures? This paper aims to quantify NUMA effects on the SGI Origin 3000 system as a prelude to answering this important question. We discuss the tools required to study NUMA effects and use them in the study of latency, bandwidth and the solution of a 2-D heat diffusion problem.
Ruibo Wang - One of the best experts on this subject based on the ideXlab platform.
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Aware conflict detection of non-uniform memory access system and prevention for transactional memory
Journal of Central South University, 2012Co-Authors: Ruibo WangAbstract:Most transactional memory (TM) research focused on multi-core processors, and others investigated at the clusters, leaving the area of non-uniform memory access (NUMA) system unexplored. The existing TM implementations made significant performance degradation on NUMA system because they ignored the slower remote memory access. To solve this problem, a latency-based conflict detection and a forecasting-based conflict prevention method were proposed. Using these techniques, the NUMA aware TM system was presented. By reducing the remote memory access and the abort rate of transaction, the experiment results show that the NUMA aware strategies present good practical TM performance on NUMA system.
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Using Transactional memory on CC-NUMA systems
2010Co-Authors: Ruibo WangAbstract:Transactional memory (TM) research has focused on multi-core processors and SMP machines; limited research has been aimed at the clusters, leaving the area of CC-NUMA(Cache Coherent non-uniform memory access) systems unexplored. The CC-NUMA system's memory is physically distributed which brings the different latency between local and remote memory access. The TMs designed for shared memory architecture are not suitable for CC-NUMA's distributed memory architecture. To be aware of the different memory access latency, we introduce a layered conflict detection strategy corresponding to the system's layer. The layered strategy provides a good practical performance on CC-NUMA systems.
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PODC - Brief announcement: NUMA-aware transactional memory
Proceeding of the 29th ACM SIGACT-SIGOPS symposium on Principles of distributed computing - PODC '10, 2010Co-Authors: Ruibo WangAbstract:Transactional memory (TM) research has focused on multi-core processors; limited research has been aimed at the clusters, leaving the area of NUMA (non-uniform memory access) system unexplored. The NUMA system's memory is physically distributed which brings the different access latency between local and remote memory. The existing TM design is not NUMA-aware which makes significant performance degradation on NUMA system. We introduce the latency-based conflict detection process and the forecasting-based conflict preventing method. The NUMA-aware strategies provide a good practical TM performance on NUMA system.
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HPDC - Investigating transactional memory performance on ccNUMA machines
Proceedings of the 18th ACM international symposium on High performance distributed computing - HPDC '09, 2009Co-Authors: Ruibo WangAbstract:Most Software Transactional memory (STM) research has focused on multi-core processors and small SMP machines; limited research has been aimed at the clusters, leaving the area of big SMP machines unexplored. Big SMP machine usually use non-uniform memory access (NUMA) to unburden the overloading between CPUs and the memory. In this paper, we evaluate several STM implementations on big SMP machine with cache coherent NUMA (ccNUMA) architecture. We found the remote memory access latency is the key factor influencing the STM performance. We also analyze the different design choices of STM. Finally, we conclude a specific design choice to achieve high performance in this domain.
Ravishankar Rao - One of the best experts on this subject based on the ideXlab platform.
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Segmented bitline cache : Exploiting non-uniform memory access patterns
Lecture Notes in Computer Science, 2006Co-Authors: Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh AkellaAbstract:On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the overall bitline capacitance. The success of this cache relies on accessing segments near the sense-amps much more often than remote segments. We show that the access pattern to the first level data and instruction cache is extremely skewed. Only a small set of cache lines are accessed frequently. We exploit this non-uniform cache access pattern by mapping the frequently accessed cache lines closer to the sense amp. These lines are isolated by segmenting circuits on the bitlines and hence dissipate lesser power when accessed. Modifications to the address decoder enable a dynamic re-mapping of cache lines to segments. In this paper, we explore the design-space of segmenting the level one data and instruction caches. Instruction and data caches show potential power savings of 10% and 6% respectively on the subset of benchmarks simulated.
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HiPC - Segmented bitline cache: exploiting non-uniform memory access patterns
High Performance Computing - HiPC 2006, 2006Co-Authors: Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh AkellaAbstract:On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the overall bitline capacitance. The success of this cache relies on accessing segments near the sense-amps much more often than remote segments. We show that the access pattern to the first level data and instruction cache is extremely skewed. Only a small set of cache lines are accessed frequently. We exploit this non-uniform cache access pattern by mapping the frequently accessed cache lines closer to the sense amp. These lines are isolated by segmenting circuits on the bitlines and hence dissipate lesser power when accessed. Modifications to the address decoder enable a dynamic re-mapping of cache lines to segments. In this paper, we explore the design-space of segmenting the level one data and instruction caches. Instruction and data caches show potential power savings of 10% and 6% respectively on the subset of benchmarks simulated.
Justin Wenck - One of the best experts on this subject based on the ideXlab platform.
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Segmented bitline cache : Exploiting non-uniform memory access patterns
Lecture Notes in Computer Science, 2006Co-Authors: Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh AkellaAbstract:On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the overall bitline capacitance. The success of this cache relies on accessing segments near the sense-amps much more often than remote segments. We show that the access pattern to the first level data and instruction cache is extremely skewed. Only a small set of cache lines are accessed frequently. We exploit this non-uniform cache access pattern by mapping the frequently accessed cache lines closer to the sense amp. These lines are isolated by segmenting circuits on the bitlines and hence dissipate lesser power when accessed. Modifications to the address decoder enable a dynamic re-mapping of cache lines to segments. In this paper, we explore the design-space of segmenting the level one data and instruction caches. Instruction and data caches show potential power savings of 10% and 6% respectively on the subset of benchmarks simulated.
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HiPC - Segmented bitline cache: exploiting non-uniform memory access patterns
High Performance Computing - HiPC 2006, 2006Co-Authors: Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh AkellaAbstract:On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the overall bitline capacitance. The success of this cache relies on accessing segments near the sense-amps much more often than remote segments. We show that the access pattern to the first level data and instruction cache is extremely skewed. Only a small set of cache lines are accessed frequently. We exploit this non-uniform cache access pattern by mapping the frequently accessed cache lines closer to the sense amp. These lines are isolated by segmenting circuits on the bitlines and hence dissipate lesser power when accessed. Modifications to the address decoder enable a dynamic re-mapping of cache lines to segments. In this paper, we explore the design-space of segmenting the level one data and instruction caches. Instruction and data caches show potential power savings of 10% and 6% respectively on the subset of benchmarks simulated.