The Experts below are selected from a list of 84 Experts worldwide ranked by ideXlab platform
Takahiro Hanyu - One of the best experts on this subject based on the ideXlab platform.
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Nonvolatile field programmable gate array using 2 transistor 1 mtj cell based multi context array for power and area efficient dynamically reconfigurable logic
Japanese Journal of Applied Physics, 2015Co-Authors: Daisuke Suzuki, Takahiro HanyuAbstract:A dynamically reconfigurable Nonvolatile field-programmable gate array (FPGA) with a multi-context (MC) cell array structure that uses three-terminal magnetic tunnel junction (MTJ) devices is proposed. The use of single-ended circuitry together with a 2-transistor and 1-MTJ (2T–1MTJ) context cell allows for the minimization of the area overhead of the context array with Nonvolatile Storage capability. As the 2T–1MTJ cell has no power line, the leakage current overhead is also minimized. With the proposed implementation, the transistor counts and leakage power during power-on are reduced by 59 and 71%, respectively, compared to the static random-access memory (SRAM)-based implementation using 40-nm CMOS technology.
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a 3 14 um 2 4t 2mtj cell fully parallel tcam based on Nonvolatile logic in memory architecture
Symposium on VLSI Circuits, 2012Co-Authors: Shoun Matsunaga, Shoji Ikeda, Tetsuo Endoh, S Miura, Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno, Takahiro HanyuAbstract:A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel Nonvolatile TCAM. By optimally merging a Nonvolatile Storage function and a comparison logic function into a TCAM cell circuit with a Nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.
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fabrication of a Nonvolatile lookup table circuit chip using magneto semiconductor hybrid structure for an immediate power up field programmable gate array
Symposium on VLSI Circuits, 2009Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, K Miura, Jun Hayakawa, Tetsuo Endoh, H Ohno, Takahiro HanyuAbstract:Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and Nonvolatile Storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.
Daisuke Suzuki - One of the best experts on this subject based on the ideXlab platform.
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fabrication of a 3000 6 input luts embedded and block level power gated Nonvolatile fpga chip using p mtj based logic in memory structure
Symposium on VLSI Circuits, 2015Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Tetsuo Endoh, S Miura, Akira Mochizuki, Hiroaki Honjo, H Sato, Shunsuke Fukami, H OhnoAbstract:A Nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to Nonvolatile Storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.
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Nonvolatile field programmable gate array using 2 transistor 1 mtj cell based multi context array for power and area efficient dynamically reconfigurable logic
Japanese Journal of Applied Physics, 2015Co-Authors: Daisuke Suzuki, Takahiro HanyuAbstract:A dynamically reconfigurable Nonvolatile field-programmable gate array (FPGA) with a multi-context (MC) cell array structure that uses three-terminal magnetic tunnel junction (MTJ) devices is proposed. The use of single-ended circuitry together with a 2-transistor and 1-MTJ (2T–1MTJ) context cell allows for the minimization of the area overhead of the context array with Nonvolatile Storage capability. As the 2T–1MTJ cell has no power line, the leakage current overhead is also minimized. With the proposed implementation, the transistor counts and leakage power during power-on are reduced by 59 and 71%, respectively, compared to the static random-access memory (SRAM)-based implementation using 40-nm CMOS technology.
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fabrication of a Nonvolatile lookup table circuit chip using magneto semiconductor hybrid structure for an immediate power up field programmable gate array
Symposium on VLSI Circuits, 2009Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, K Miura, Jun Hayakawa, Tetsuo Endoh, H Ohno, Takahiro HanyuAbstract:Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and Nonvolatile Storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.
Shoji Ikeda - One of the best experts on this subject based on the ideXlab platform.
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fabrication of a 3000 6 input luts embedded and block level power gated Nonvolatile fpga chip using p mtj based logic in memory structure
Symposium on VLSI Circuits, 2015Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Tetsuo Endoh, S Miura, Akira Mochizuki, Hiroaki Honjo, H Sato, Shunsuke Fukami, H OhnoAbstract:A Nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to Nonvolatile Storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.
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a 3 14 um 2 4t 2mtj cell fully parallel tcam based on Nonvolatile logic in memory architecture
Symposium on VLSI Circuits, 2012Co-Authors: Shoun Matsunaga, Shoji Ikeda, Tetsuo Endoh, S Miura, Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno, Takahiro HanyuAbstract:A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel Nonvolatile TCAM. By optimally merging a Nonvolatile Storage function and a comparison logic function into a TCAM cell circuit with a Nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.
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fabrication of a Nonvolatile lookup table circuit chip using magneto semiconductor hybrid structure for an immediate power up field programmable gate array
Symposium on VLSI Circuits, 2009Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, K Miura, Jun Hayakawa, Tetsuo Endoh, H Ohno, Takahiro HanyuAbstract:Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and Nonvolatile Storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.
Tetsuo Endoh - One of the best experts on this subject based on the ideXlab platform.
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fabrication of a 3000 6 input luts embedded and block level power gated Nonvolatile fpga chip using p mtj based logic in memory structure
Symposium on VLSI Circuits, 2015Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Tetsuo Endoh, S Miura, Akira Mochizuki, Hiroaki Honjo, H Sato, Shunsuke Fukami, H OhnoAbstract:A Nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to Nonvolatile Storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.
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a 3 14 um 2 4t 2mtj cell fully parallel tcam based on Nonvolatile logic in memory architecture
Symposium on VLSI Circuits, 2012Co-Authors: Shoun Matsunaga, Shoji Ikeda, Tetsuo Endoh, S Miura, Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno, Takahiro HanyuAbstract:A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel Nonvolatile TCAM. By optimally merging a Nonvolatile Storage function and a comparison logic function into a TCAM cell circuit with a Nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.
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fabrication of a Nonvolatile lookup table circuit chip using magneto semiconductor hybrid structure for an immediate power up field programmable gate array
Symposium on VLSI Circuits, 2009Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, K Miura, Jun Hayakawa, Tetsuo Endoh, H Ohno, Takahiro HanyuAbstract:Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and Nonvolatile Storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.
H Ohno - One of the best experts on this subject based on the ideXlab platform.
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fabrication of a 3000 6 input luts embedded and block level power gated Nonvolatile fpga chip using p mtj based logic in memory structure
Symposium on VLSI Circuits, 2015Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Tetsuo Endoh, S Miura, Akira Mochizuki, Hiroaki Honjo, H Sato, Shunsuke Fukami, H OhnoAbstract:A Nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to Nonvolatile Storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.
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fabrication of a Nonvolatile lookup table circuit chip using magneto semiconductor hybrid structure for an immediate power up field programmable gate array
Symposium on VLSI Circuits, 2009Co-Authors: Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, K Miura, Jun Hayakawa, Tetsuo Endoh, H Ohno, Takahiro HanyuAbstract:Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and Nonvolatile Storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.
