The Experts below are selected from a list of 93 Experts worldwide ranked by ideXlab platform
Juan Antonio Maestro - One of the best experts on this subject based on the ideXlab platform.
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reduction of parity overhead in a subset of Orthogonal Latin Square codes
Conference on Design of Circuits and Integrated Systems, 2020Co-Authors: Pedro Reviriego, Alfonso Sanchezmacian, Shanshan Liu, Liyi Xiao, Juan Antonio MaestroAbstract:Radiation may cause unexpected effects in electronics, in particular in harsh environments such as Space. Error correcting codes can be used to mitigate radiation effects in these scenarios. Orthogonal Latin Square (OLS) codes are a type of error-correction codes (ECC) capable of correcting multiple bit errors. They can be decoded with low delay and complexity. Therefore, they are of interest in communications and memory applications. Their main drawback is the overhead required in terms of parity bits needed to protect the information. Thus, a relevant goal is to reduce the number of parity bits while keeping the simplicity and delay properties. This paper presents a method to limit this overhead with similar delay and complexity characteristics with respect to the original code.
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reliability of 3d memories using Orthogonal Latin Square codes
Microelectronics Reliability, 2019Co-Authors: Alfonso Sanchezmacian, Francisco Garciaherrero, Juan Antonio MaestroAbstract:Abstract Radiation is a cause of errors in electronics systems, especially on those deployed in space. Memories can suffer from different radiation effects including Single Event Upsets and Multiple Cell Upsets. These effects produce corruption of data and may cause a system malfunction. 3D die-stacked memories have been designed to increase bandwidth, reduce latency and limit power consumption. The shielding characteristic of the 3D structure causes a heterogeneous fault tolerance behaviour of the system where some of the inner dies are invulnerable while the outer dies require different protection levels. Orthogonal Latin Square codes are a class of error correcting codes that are modular and can provide different error correction degrees depending on the number of parity bits used. This paper proposed a solution based on current standards to provide dynamic and heterogeneous error correction capabilities to a 3D memory. To do so, Orthogonal Latin Square codes are used.
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comments on extend Orthogonal Latin Square codes for 32 bit data protection in memory applications microelectron reliab 63 278 283 2016
Microelectronics Reliability, 2017Co-Authors: Shanshan Liu, Alfonso Sanchezmacian, Juan Antonio Maestro, Pedro Reviriego, Liyi XiaoAbstract:Abstract Additional extended Orthogonal Latin Square codes to protect 32-bit data words are presented. The new codes require less parity bits than the ones presented in the original paper at the cost of a moderate overhead in encoding and decoding complexity.
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A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes
IEEE Transactions on Reliability, 2017Co-Authors: Pedro Reviriego, Shanshan Liu, Alfonso Sanchez-macian, Liyi Xiao, Juan Antonio MaestroAbstract:The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin Square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to Orthogonal Latin Square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard Orthogonal Latin Square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.
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combined seu and sefi protection for memories using Orthogonal Latin Square codes
IEEE Transactions on Circuits and Systems, 2016Co-Authors: Alfonso Sanchezmacian, Pedro Reviriego, Juan Antonio MaestroAbstract:Radiation effects cause several types of errors on memories including single event upsets (SEUs) or single event functional interrupts (SEFIs). Error correction codes (ECCs) are widely used to protect against those errors. For a number of reasons, there is a large interest in using double data rate type three (DDR-3) synchronous dynamic random-access (SDRAM) memories in space applications. Radiation testing results show that these memories will suffer both SEUs and SEFIs when used in space. Protection against a SEFI and an SEU is needed to achieve high reliability. In this paper, a method to protect 16-bit and 64-bit data word memories composed of 8-bit memory devices against a simultaneous SEFI and an SEU is presented. The scheme uses Orthogonal Latin Square (OLS) codes and can be activated when a SEFI occurs, using a conventional double error correction approach otherwise.
Pedro Reviriego - One of the best experts on this subject based on the ideXlab platform.
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reduction of parity overhead in a subset of Orthogonal Latin Square codes
Conference on Design of Circuits and Integrated Systems, 2020Co-Authors: Pedro Reviriego, Alfonso Sanchezmacian, Shanshan Liu, Liyi Xiao, Juan Antonio MaestroAbstract:Radiation may cause unexpected effects in electronics, in particular in harsh environments such as Space. Error correcting codes can be used to mitigate radiation effects in these scenarios. Orthogonal Latin Square (OLS) codes are a type of error-correction codes (ECC) capable of correcting multiple bit errors. They can be decoded with low delay and complexity. Therefore, they are of interest in communications and memory applications. Their main drawback is the overhead required in terms of parity bits needed to protect the information. Thus, a relevant goal is to reduce the number of parity bits while keeping the simplicity and delay properties. This paper presents a method to limit this overhead with similar delay and complexity characteristics with respect to the original code.
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comments on extend Orthogonal Latin Square codes for 32 bit data protection in memory applications microelectron reliab 63 278 283 2016
Microelectronics Reliability, 2017Co-Authors: Shanshan Liu, Alfonso Sanchezmacian, Juan Antonio Maestro, Pedro Reviriego, Liyi XiaoAbstract:Abstract Additional extended Orthogonal Latin Square codes to protect 32-bit data words are presented. The new codes require less parity bits than the ones presented in the original paper at the cost of a moderate overhead in encoding and decoding complexity.
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A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes
IEEE Transactions on Reliability, 2017Co-Authors: Pedro Reviriego, Shanshan Liu, Alfonso Sanchez-macian, Liyi Xiao, Juan Antonio MaestroAbstract:The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin Square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to Orthogonal Latin Square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard Orthogonal Latin Square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.
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combined seu and sefi protection for memories using Orthogonal Latin Square codes
IEEE Transactions on Circuits and Systems, 2016Co-Authors: Alfonso Sanchezmacian, Pedro Reviriego, Juan Antonio MaestroAbstract:Radiation effects cause several types of errors on memories including single event upsets (SEUs) or single event functional interrupts (SEFIs). Error correction codes (ECCs) are widely used to protect against those errors. For a number of reasons, there is a large interest in using double data rate type three (DDR-3) synchronous dynamic random-access (SDRAM) memories in space applications. Radiation testing results show that these memories will suffer both SEUs and SEFIs when used in space. Protection against a SEFI and an SEU is needed to achieve high reliability. In this paper, a method to protect 16-bit and 64-bit data word memories composed of 8-bit memory devices against a simultaneous SEFI and an SEU is presented. The scheme uses Orthogonal Latin Square (OLS) codes and can be activated when a SEFI occurs, using a conventional double error correction approach otherwise.
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unequal error protection codes derived from double error correction Orthogonal Latin Square codes
IEEE Transactions on Computers, 2016Co-Authors: Mustafa Demirci, Pedro Reviriego, Juan Antonio MaestroAbstract:In recent years, there has been a growing interest in multi-bit error correction codes (ECCs) to protect SRAM memories. This has been caused by the increased number of multiple errors that memories suffer as technology scales. To be suitable to protect an SRAM memory, an ECC has to be decodable in parallel and with low latency. Among the codes proposed for memory protection are Orthogonal Latin Square (OLS) codes that provide low latency decoding and a modular construction. For some applications, like multimedia or signal processing, the effect of errors on the memory bits can be very different depending on their position on the word. Therefore, in these cases, it is more effective to provide different degrees of error correction for the different bits. This is done with unequal error protection (UEP) codes. In this paper, UEP codes are derived from double error correction (DEC) OLS codes. The derived codes are implemented for an FPGA platform to evaluate the decoder complexity and latency. The results show that the new codes can be implemented with lower decoding delay than traditional SEC-DED codes and with a cost similar to that of both DEC OLS and SEC-DED codes.
Shanshan Liu - One of the best experts on this subject based on the ideXlab platform.
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reduction of parity overhead in a subset of Orthogonal Latin Square codes
Conference on Design of Circuits and Integrated Systems, 2020Co-Authors: Pedro Reviriego, Alfonso Sanchezmacian, Shanshan Liu, Liyi Xiao, Juan Antonio MaestroAbstract:Radiation may cause unexpected effects in electronics, in particular in harsh environments such as Space. Error correcting codes can be used to mitigate radiation effects in these scenarios. Orthogonal Latin Square (OLS) codes are a type of error-correction codes (ECC) capable of correcting multiple bit errors. They can be decoded with low delay and complexity. Therefore, they are of interest in communications and memory applications. Their main drawback is the overhead required in terms of parity bits needed to protect the information. Thus, a relevant goal is to reduce the number of parity bits while keeping the simplicity and delay properties. This paper presents a method to limit this overhead with similar delay and complexity characteristics with respect to the original code.
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comments on extend Orthogonal Latin Square codes for 32 bit data protection in memory applications microelectron reliab 63 278 283 2016
Microelectronics Reliability, 2017Co-Authors: Shanshan Liu, Alfonso Sanchezmacian, Juan Antonio Maestro, Pedro Reviriego, Liyi XiaoAbstract:Abstract Additional extended Orthogonal Latin Square codes to protect 32-bit data words are presented. The new codes require less parity bits than the ones presented in the original paper at the cost of a moderate overhead in encoding and decoding complexity.
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A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes
IEEE Transactions on Reliability, 2017Co-Authors: Pedro Reviriego, Shanshan Liu, Alfonso Sanchez-macian, Liyi Xiao, Juan Antonio MaestroAbstract:The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin Square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to Orthogonal Latin Square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard Orthogonal Latin Square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.
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extend Orthogonal Latin Square codes for 32 bit data protection in memory applications
Microelectronics Reliability, 2016Co-Authors: Shanshan Liu, Liyi Xiao, Zhigang MaoAbstract:Abstract As CMOS technology size scales down, multiple cell upsets (MCUs) caused by a single radiation particle have become one of the most challenging reliability issues for memories used in space application. Error correction codes (ECCs) are commonly used to protect memories against errors. Single error correction-Double error detection (SEC-DED) codes are the simplest and most typical ones, but they can only corrected single errors. The advanced ECCs, which can provide enough protection for memories, cost more overhead due to their complex decoders. Orthogonal Latin Square (OLS) codes are one type of one-step majority logic decodable (OS-MLD) codes that can be decoded with low complexity and delay. However, there are no OLS codes directly fitting 32-bit data, which is a typical data size in memories. In this paper, (55, 32) and (68, 32) codes derived from (45, 25) and (55, 25) OLS codes have been proposed in order to improve OLS codes in terms of protection for the 32-bit data. The proposed codes can maintain the correction capability of OLS codes and be decoded with low delay and complexity. The evaluation of the implementations for these codes are presented and compared with those of the shortened version (60, 32) and (76, 32) OLS codes. The results show that the area and power of a 2-bit MCUs immune radiation hardened SRAM that protected by the proposed codes have been reduced by 7.76% and 6.34%, respectively. In the case of a 3-bit MCUs immune, the area and power of whole circuits have been reduced by 8.82% and 4.56% when the proposed codes are used.
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Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes
IEEE Transactions on Device and Materials Reliability, 2016Co-Authors: Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio MaestroAbstract:As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a growing interest on error correction codes that can correct multibit errors. Orthogonal Latin Square (OLS) codes are an interesting option due to their low-complexity decoding and modular construction. Several works have also shown that it is possible to improve OLS codes, for example, by providing additional error correction for adjacent errors. In particular, a method has been recently proposed to implement triple adjacent error correction (TAEC) on double error correction (DEC) OLS codes. That scheme exploits the properties of OLS codes to achieve TAEC using an independent error correction logic and does not require additional parity check bits. This can be useful as, in many cases, the errors caused by MCUs are adjacent. In this paper, a more efficient technique to implement TAEC for DEC OLS codes is presented. The proposed method can be used as long as there are sufficient parity check bits to interleave among the data bits. This is the case for DEC OLS codes of up to 64 bits, which can be used to protect 16- and 64-bit data words. The new scheme uses an optimized bit placement that interleaves data and parity check bits to simplify the decoding. In particular, correction of single, double, and triple adjacent errors is now achieved with a single circuit that is a minor modification of the standard OLS decoding. This reduces area, power, and delay, making the new scheme attractive for circuit implementations.
Liyi Xiao - One of the best experts on this subject based on the ideXlab platform.
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reduction of parity overhead in a subset of Orthogonal Latin Square codes
Conference on Design of Circuits and Integrated Systems, 2020Co-Authors: Pedro Reviriego, Alfonso Sanchezmacian, Shanshan Liu, Liyi Xiao, Juan Antonio MaestroAbstract:Radiation may cause unexpected effects in electronics, in particular in harsh environments such as Space. Error correcting codes can be used to mitigate radiation effects in these scenarios. Orthogonal Latin Square (OLS) codes are a type of error-correction codes (ECC) capable of correcting multiple bit errors. They can be decoded with low delay and complexity. Therefore, they are of interest in communications and memory applications. Their main drawback is the overhead required in terms of parity bits needed to protect the information. Thus, a relevant goal is to reduce the number of parity bits while keeping the simplicity and delay properties. This paper presents a method to limit this overhead with similar delay and complexity characteristics with respect to the original code.
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comments on extend Orthogonal Latin Square codes for 32 bit data protection in memory applications microelectron reliab 63 278 283 2016
Microelectronics Reliability, 2017Co-Authors: Shanshan Liu, Alfonso Sanchezmacian, Juan Antonio Maestro, Pedro Reviriego, Liyi XiaoAbstract:Abstract Additional extended Orthogonal Latin Square codes to protect 32-bit data words are presented. The new codes require less parity bits than the ones presented in the original paper at the cost of a moderate overhead in encoding and decoding complexity.
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A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes
IEEE Transactions on Reliability, 2017Co-Authors: Pedro Reviriego, Shanshan Liu, Alfonso Sanchez-macian, Liyi Xiao, Juan Antonio MaestroAbstract:The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin Square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to Orthogonal Latin Square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard Orthogonal Latin Square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.
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extend Orthogonal Latin Square codes for 32 bit data protection in memory applications
Microelectronics Reliability, 2016Co-Authors: Shanshan Liu, Liyi Xiao, Zhigang MaoAbstract:Abstract As CMOS technology size scales down, multiple cell upsets (MCUs) caused by a single radiation particle have become one of the most challenging reliability issues for memories used in space application. Error correction codes (ECCs) are commonly used to protect memories against errors. Single error correction-Double error detection (SEC-DED) codes are the simplest and most typical ones, but they can only corrected single errors. The advanced ECCs, which can provide enough protection for memories, cost more overhead due to their complex decoders. Orthogonal Latin Square (OLS) codes are one type of one-step majority logic decodable (OS-MLD) codes that can be decoded with low complexity and delay. However, there are no OLS codes directly fitting 32-bit data, which is a typical data size in memories. In this paper, (55, 32) and (68, 32) codes derived from (45, 25) and (55, 25) OLS codes have been proposed in order to improve OLS codes in terms of protection for the 32-bit data. The proposed codes can maintain the correction capability of OLS codes and be decoded with low delay and complexity. The evaluation of the implementations for these codes are presented and compared with those of the shortened version (60, 32) and (76, 32) OLS codes. The results show that the area and power of a 2-bit MCUs immune radiation hardened SRAM that protected by the proposed codes have been reduced by 7.76% and 6.34%, respectively. In the case of a 3-bit MCUs immune, the area and power of whole circuits have been reduced by 8.82% and 4.56% when the proposed codes are used.
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Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes
IEEE Transactions on Device and Materials Reliability, 2016Co-Authors: Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio MaestroAbstract:As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a growing interest on error correction codes that can correct multibit errors. Orthogonal Latin Square (OLS) codes are an interesting option due to their low-complexity decoding and modular construction. Several works have also shown that it is possible to improve OLS codes, for example, by providing additional error correction for adjacent errors. In particular, a method has been recently proposed to implement triple adjacent error correction (TAEC) on double error correction (DEC) OLS codes. That scheme exploits the properties of OLS codes to achieve TAEC using an independent error correction logic and does not require additional parity check bits. This can be useful as, in many cases, the errors caused by MCUs are adjacent. In this paper, a more efficient technique to implement TAEC for DEC OLS codes is presented. The proposed method can be used as long as there are sufficient parity check bits to interleave among the data bits. This is the case for DEC OLS codes of up to 64 bits, which can be used to protect 16- and 64-bit data words. The new scheme uses an optimized bit placement that interleaves data and parity check bits to simplify the decoding. In particular, correction of single, double, and triple adjacent errors is now achieved with a single circuit that is a minor modification of the standard OLS decoding. This reduces area, power, and delay, making the new scheme attractive for circuit implementations.
N. Gautham - One of the best experts on this subject based on the ideXlab platform.
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A new peptide docking strategy using a mean field technique with mutually Orthogonal Latin Square sampling
Journal of Computer-Aided Molecular Design, 2008Co-Authors: P. Arun Prasad, N. GauthamAbstract:The theoretical prediction of the association of a flexible ligand with a protein receptor requires efficient sampling of the conformational space of the ligand. Several docking methodologies are currently available. We propose a new docking technique that performs well at low computational cost. The method uses mutually Orthogonal Latin Squares to efficiently sample the docking space. A variant of the mean field technique is used to analyze this sample to arrive at the optimum. The method has been previously applied to explore the conformational space of peptides and identify structures with low values for the potential energy. Here we extend this method to simultaneously identify both the low energy conformation as well as a ‘high-scoring’ docking mode. Application of the method to 56 protein–peptide complexes, in which the length of the peptide ligand ranges from three to seven residues, and comparisons with Autodock 3.05, showed that the method works well.
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exploring the conformational space of protein loops using a mean field technique with mols sampling
Proteins, 2007Co-Authors: V Kanagasabai, Arun P Prasad, Jothi Arunachalam, N. GauthamAbstract:We have recently developed a computational technique that uses mutually Orthogonal Latin Square sampling to explore the conformational space of oligopeptides in an exhaustive manner. In this article, we report its use to analyze the conformational spaces of 120 protein loop sequences in proteins, culled from the PDB, having the length ranging from 5 to 10 residues. The force field used did not have any information regarding the sequences or structures that flanked the loop. The results of the analyses show that the native structure of the loop, as found in the PDB falls at one of the low energy points in the conformational landscape of the sequences. Thus, a large portion of the structural determinants of the loop may be considered intrinsic to the sequence, regardless of either adjacent sequences or structures, or the interactions that the atoms of the loop make with other residues in the protein or in neighboring proteins. Proteins 2007. © 2007 Wiley-Liss, Inc.