The Experts below are selected from a list of 3102 Experts worldwide ranked by ideXlab platform
Brian D. Sierawski - One of the best experts on this subject based on the ideXlab platform.
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electron induced Single Event Upsets in 28 nm and 45 nm bulk srams
IEEE Transactions on Nuclear Science, 2015Co-Authors: James M Trippe, Brian D. Sierawski, Robert A. Weller, M. P. King, R. A. Reed, B. Narasimham, Rebekah Austin, Erik D Funkhouser, B Bartz, Robert BaumannAbstract:In this study, we present experimental evidence of Single electron-induced Upsets in commercial 28 nm and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in both technology nodes when the SRAM was operated in a low power state. The experimental cross section depends strongly on both bias and technology node feature size, consistent with previous work in which SRAMs were irradiated with low energy muons and protons. Accompanying simulations demonstrate that δ-rays produced by the primary electrons are responsible for the observed Upsets. Additional simulations predict the on-orbit Event rates for various Earth and Jovian environments for a set of sensitive volumes representative of current technology nodes. The electron contribution to the total upset rate for Earth environments is significant for critical charges as high as 0.2 fC. This value is comparable to that of sub-22 nm bulk SRAMs. Similarly, for the Jovian environment, the electron-induced upset rate is larger than the proton-induced upset rate for critical charges as high as 0.3 fC.
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Bias dependence of muon-induced Single Event Upsets in 28 nm static random access memories
2014 IEEE International Reliability Physics Symposium, 2014Co-Authors: Brian D. Sierawski, Michael Trinczek, Bharat Bhuva, Robert Reed, Balaji Narasimham, Katsuhiko Ishida, Adrian Hillier, Ewart Blackmore, Richard WongAbstract:Experiments performed at TRIUMF and the Rutherford Appleton ISIS facility demonstrate the bias dependence of muon-induced Single Event Upsets in delidded 28 nm static random access memories. Increased probability for upset is observed for memories operating at reduced voltages. Fully packaged parts are shown to be suitable to screen for low-energy muon sensitivity.
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effects of multi node charge collection in flip flop designs at advanced technology nodes
International Reliability Physics Symposium, 2010Co-Authors: Vijay B Sheshadri, Brian D. Sierawski, Marcus H. Mendenhall, Robert A. Weller, R. A. Reed, R. D. Schrimpf, B L Bhuva, Shijie Wen, K M Warren, R WongAbstract:Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of Single-Event Upsets in advanced technologies due to multi-node charge collection from Single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment with Monte-Carlo simulations of charge generation in several technology generations.
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Muon-Induced Single Event Upsets in Deep-Submicron Technology
IEEE Transactions on Nuclear Science, 2010Co-Authors: Brian D. Sierawski, Marcus H. Mendenhall, Robert A. Reed, Michael A. Clemens, Robert A. Weller, Ronald D. Schrimpf, Ewart W. Blackmore, Michael Trinczek, Bassam Hitti, Jonathan A. PellishAbstract:Experimental data are presented that show low-energy muons are able to cause Single Event Upsets in 65 nm, 45 nm, and 40 nm CMOS SRAMs. Energy deposition measurements using a surface barrier detector are presented to characterize the kinetic energy spectra produced by the M20B surface muon beam at TRIUMF. A Geant4 application is used to simulate the beam and estimate the energy spectra incident on the memories. Results indicate that the sensitivity to this mechanism will increase for scaled technologies.
Richard Wong - One of the best experts on this subject based on the ideXlab platform.
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effects of threshold voltage variations on Single Event upset response of sequential circuits at advanced technology nodes
IEEE Transactions on Nuclear Science, 2017Co-Authors: Hangfang Zhang, B. Narasimham, L W Massengill, B L Bhuva, H Jiang, T R Assis, N N Mahatme, Shijie Wen, Richard WongAbstract:Threshold voltage ( ${V}_{T}$ ) of transistors plays an important role in Single-Event Upsets (SEU) and system power consumption. Effect of $\text{V}_{\text {T}}$ on Single-Event Upsets can be very different for different technologies. SEU responses of flip-flops and logic circuits in 20-nm bulk planar and 16-nm bulk FinFET technologies with different $\text{V}_{\text {T}}$ options are investigated. Results show that for the 20-nm bulk planar technology, the design with the highest threshold voltage among all $\text{V}_{\text {T}}$ options shows the lowest SEU cross-section for alpha particle irradiation. For the 16-nm FinFET technology, the option with the highest threshold voltage shows the highest SEU cross-section. As frequency increases, the SEU cross-section of the highest $\text{V}_{\text {T}}$ design shows a faster increase and a larger curve slope due to increased Single-Event transient (SET) pulse width compared to the lower $\text{V}_{\text {T}}$ designs for the 16-nm FinFET technology node.
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Bias dependence of muon-induced Single Event Upsets in 28 nm static random access memories
2014 IEEE International Reliability Physics Symposium, 2014Co-Authors: Brian D. Sierawski, Michael Trinczek, Bharat Bhuva, Robert Reed, Balaji Narasimham, Katsuhiko Ishida, Adrian Hillier, Ewart Blackmore, Richard WongAbstract:Experiments performed at TRIUMF and the Rutherford Appleton ISIS facility demonstrate the bias dependence of muon-induced Single Event Upsets in delidded 28 nm static random access memories. Increased probability for upset is observed for memories operating at reduced voltages. Fully packaged parts are shown to be suitable to screen for low-energy muon sensitivity.
B L Bhuva - One of the best experts on this subject based on the ideXlab platform.
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effects of threshold voltage variations on Single Event upset response of sequential circuits at advanced technology nodes
IEEE Transactions on Nuclear Science, 2017Co-Authors: Hangfang Zhang, B. Narasimham, L W Massengill, B L Bhuva, H Jiang, T R Assis, N N Mahatme, Shijie Wen, Richard WongAbstract:Threshold voltage ( ${V}_{T}$ ) of transistors plays an important role in Single-Event Upsets (SEU) and system power consumption. Effect of $\text{V}_{\text {T}}$ on Single-Event Upsets can be very different for different technologies. SEU responses of flip-flops and logic circuits in 20-nm bulk planar and 16-nm bulk FinFET technologies with different $\text{V}_{\text {T}}$ options are investigated. Results show that for the 20-nm bulk planar technology, the design with the highest threshold voltage among all $\text{V}_{\text {T}}$ options shows the lowest SEU cross-section for alpha particle irradiation. For the 16-nm FinFET technology, the option with the highest threshold voltage shows the highest SEU cross-section. As frequency increases, the SEU cross-section of the highest $\text{V}_{\text {T}}$ design shows a faster increase and a larger curve slope due to increased Single-Event transient (SET) pulse width compared to the lower $\text{V}_{\text {T}}$ designs for the 16-nm FinFET technology node.
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bias dependence of Single Event Upsets in 16 nm finfet d flip flops
IEEE Transactions on Nuclear Science, 2015Co-Authors: B. Narasimham, R. D. Schrimpf, J. K. Wang, B L Bhuva, Safar Hatami, Ali Anvar, David Harris, Alvin Lai Lin, Indranil Chatterjee, R. A. ReedAbstract:With fabrication processes migrating from planar devices to FinFETs, the differences in physical structure necessitate evaluating the SEU mechanisms of FinFET-based circuits. Since FinFET-based bi-stable circuits have shown better stability at low supply voltages and hence improved power dissipation, it is also necessary to assess the SEU performance over a range of voltages. In this work, the SEU cross section of FinFET-based D-flip-flops was measured with alpha particles, protons, neutrons, and heavy-ions. Results show a strong exponential increase in the SEU rate with reduction in bias for low-LET particles. Technology Computer Aided Design (TCAD) simulations show that the weak variation of collected charge with supply voltage, combined with the standard bias dependence of critical charge, is responsible for this trend.
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effects of multi node charge collection in flip flop designs at advanced technology nodes
International Reliability Physics Symposium, 2010Co-Authors: Vijay B Sheshadri, Brian D. Sierawski, Marcus H. Mendenhall, Robert A. Weller, R. A. Reed, R. D. Schrimpf, B L Bhuva, Shijie Wen, K M Warren, R WongAbstract:Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of Single-Event Upsets in advanced technologies due to multi-node charge collection from Single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment with Monte-Carlo simulations of charge generation in several technology generations.
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Single Event Upsets in deep submicrometer technologies due to charge sharing
IEEE Transactions on Device and Materials Reliability, 2008Co-Authors: O A Amusan, A. L. Sternberg, L W Massengill, M P Baze, A F Witulski, B L Bhuva, J D BlackAbstract:Circuit and 3D technology computer aided design mixed-mode simulations show that the Single Event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a Single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.
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directional sensitivity of Single Event Upsets in 90 nm cmos due to charge sharing
IEEE Transactions on Nuclear Science, 2007Co-Authors: O A Amusan, A. L. Sternberg, L W Massengill, M P Baze, A F Witulski, B L Bhuva, S Dasgupta, P R Fleming, C C Heath, M L AllesAbstract:Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.
Masanori Hashimoto - One of the best experts on this subject based on the ideXlab platform.
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muon induced Single Event Upsets in 20 nm srams comparative characterization with neutrons and alpha particles
IEEE Transactions on Nuclear Science, 2021Co-Authors: Takashi Kato, Motonobu Tampo, Masanori Hashimoto, Soshi Takeshita, Hiroki Tanaka, Hideya Matsuyama, Yasuhiro MiyakeAbstract:Negative and positive muon-induced Single-Event Upsets (SEUs) are studied in 20-nm bulk planar SRAMs. Muon irradiation is performed using a mono-energetic source with varying the muon energy. The energy dependence of the cross sections (CSs) of SEUs and multiple-cell Upsets (MCUs) shows the significant contribution of muon capture reactions for the negative muon, as reported in previous studies. Interestingly, MCU Events are found for the positive muon, in contrast to the previous studies. The CSs for the negative and positive muons are compared with that for the other terrestrial radiations: high-energy neutrons, thermal neutrons, and alpha particles. The voltage dependence of the SEU CS, together with the empirical model for charge collection, demonstrates the difference in the contributing secondary ions among the negative muon, the high-energy neutron, and the thermal neutron. The MCU Events are thoroughly analyzed in terms of their ratio to the total Events and their fail bit patterns. The results reveal that the MCU characteristics for the negative muon are different from that for the other terrestrial radiations due to the muon capture reactions, where parasitic bipolar effects and the isotropic emission of secondary ions are important factors.
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angular sensitivity of neutron induced Single Event Upsets in 12 nm finfet srams with comparison to 20 nm planar srams
IEEE Transactions on Nuclear Science, 2020Co-Authors: Takashi Kato, Masanori Hashimoto, Hideya MatsuyamaAbstract:The angular sensitivity of neutron-induced Single-Event Upsets (SEUs) is studied in 12-nm FinFET SRAMs. Irradiation experiments are performed using a terrestrial environment-compatible source with varying incidence angles. The analyses of the occurrence rates of SEUs and multiple-bit Upsets (MBUs) demonstrate that although the SEU rate decreases at grazing incidence, the MBU rate increases when the incidence direction is parallel to the word lines (WLs) of the SRAM array, as similarly observed in our previous experiments for 20-nm planar SRAMs. It is found that the angular response of multiple-cell Upsets (MCUs) is different between the 12-nm FinFET and 20-nm planar SRAMs. The comparative analysis of the voltage dependence of the MCU ratio reveals that this difference is due to the different contribution of parasitic bipolar effects (PBEs), which are more significant in the 20-nm planar SRAMs. It is also indicated that in the 12-nm FinFET SRAMs, the contribution of PBEs is relatively large when the incidence angle is parallel to the WLs. Through the characterization of the MCU Events, the validity of this picture is confirmed based on the voltage dependence of the pattern-wise MCU ratio with the consideration of the impact of PBEs on fail bit patterns.
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impact of hydrided and non hydrided materials near transistors on neutron induced Single Event Upsets
International Reliability Physics Symposium, 2020Co-Authors: Shinichiro Abe, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Tatsuhiko Sato, Junya Kuroda, Kojiro Ito, Masahide Harada, Kenichi OikawaAbstract:The impacts of hydrided and non-hydrided materials near transistors on neutron-induced Single Event Upsets (SEUs) were investigated by simulating monoenergetic neutron irradiations on 65-nm technology bulk static random access memories. The onset energy of the SEUs induced by H ions depends on the shielding capability, i.e., the material and thickness, of components placed in front of transistors when those components do not contain hydrogen atoms. The shielding capability also influences the initial slope observed in the energy-dependence of SEU cross sections. Taking into account the non-hydrided component attached to memory cells used in the simulation, all experimental data measured at each neutron facility were reproduced well using SEU cross sections obtained by simulation. We also find that the effect of components near transistors on neutron-induced soft error rates is not negligible even for irradiation by white neutrons.
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Measurement of Single-Event Upsets in 65-nm SRAMs Under Irradiation of Spallation Neutrons at J-PARC MLF
IEEE Transactions on Nuclear Science, 2020Co-Authors: Junya Kuroda, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Shinichiro Abe, Kojiro Ito, Masahide Harada, Kenichi Oikawa, Yasuhiro MiyakeAbstract:A neutron irradiation test of static random access memories (SRAMs) was performed using a spallation neutron source at Materials and Life Science Experimental Facility (MLF) in the Japan Proton Accelerator Research Complex (J-PARC). The probability of neutron-induced Single-Event Upsets (SEUs) was measured for 65-nm bulk and silicon on thin buried oxide (SOTB) SRAMs under neutron irradiation at the BL10 experimental facility. The measured SEU data were compared with the previous data of the same SRAMs which were measured at other irradiation facilities having different neutron spectra. The differences in the operating voltage dependence of the measured SEU probabilities are discussed with particular attention to the impact of irradiation side on SEUs. The particle and heavy ion transport code system (PHITS) simulation based on the simple sensitive volume model qualitatively reproduced the operating voltage dependence seen in the measured ratio of SEUs for the Bulk SRAM between the resin side and board side irradiations under different neutron fields.
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impact of irradiation side on neutron induced Single Event Upsets in 65 nm bulk srams
IEEE Transactions on Nuclear Science, 2019Co-Authors: Shinichiro Abe, Seiya Manabe, Wang Liao, Masanori Hashimoto, Tatsuhiko Sato, Yukinobu WatanabeAbstract:The impact of the irradiation side on the cross sections of Single-Event Upsets (SEUs) induced by neutrons was investigated by performing neutron irradiation measurements and simulations. A test board equipped with 65-nm bulk 6-T CMOS static random access memories was irradiated by quasi-monoenergetic neutrons, and the number of SEUs was counted. The number of SEUs obtained by the board-side irradiation was approximately 20% to 30% smaller than that obtained by irradiation on the plastic package side. We also investigated the impact of irradiation side on the soft error rates (SERs) obtained with by the terrestrial neutron energy spectrum via a Monte Carlo simulation. The SER obtained from the plastic package side irradiation was approximately twice that obtained for the board side irradiation, indicating that SERs can be reduced by equipping the device with the package side facing downward. Additionally, based on the simulation, the atomic composition of the material placed in front of the memory chip has a considerable influence on the SER because production yields and angular distributions of secondary H and He ions (the main causes of SEUs) depend on the composition. In particular, the existence of hydrides, such as plastic, considerably increases the SER because of the higher production yields of secondary H ions that are generated via elastic scattering of neutrons with hydrogen atoms.
Robert Baumann - One of the best experts on this subject based on the ideXlab platform.
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electron induced Single Event Upsets in 28 nm and 45 nm bulk srams
IEEE Transactions on Nuclear Science, 2015Co-Authors: James M Trippe, Brian D. Sierawski, Robert A. Weller, M. P. King, R. A. Reed, B. Narasimham, Rebekah Austin, Erik D Funkhouser, B Bartz, Robert BaumannAbstract:In this study, we present experimental evidence of Single electron-induced Upsets in commercial 28 nm and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in both technology nodes when the SRAM was operated in a low power state. The experimental cross section depends strongly on both bias and technology node feature size, consistent with previous work in which SRAMs were irradiated with low energy muons and protons. Accompanying simulations demonstrate that δ-rays produced by the primary electrons are responsible for the observed Upsets. Additional simulations predict the on-orbit Event rates for various Earth and Jovian environments for a set of sensitive volumes representative of current technology nodes. The electron contribution to the total upset rate for Earth environments is significant for critical charges as high as 0.2 fC. This value is comparable to that of sub-22 nm bulk SRAMs. Similarly, for the Jovian environment, the electron-induced upset rate is larger than the proton-induced upset rate for critical charges as high as 0.3 fC.
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impact of Single Event Upsets in deep submicron silicon technology
Mrs Bulletin, 2003Co-Authors: Robert BaumannAbstract:The once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability- failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.
