The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Chenchang Zhan - One of the best experts on this subject based on the ideXlab platform.
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a 0 035mm2 150ma fast response low dropout regulator based on matching enhanced error amplifier and multi threshold controlled unity gain buffer in 0 13μm cmos
International Symposium on Circuits and Systems, 2016Co-Authors: Chenchang Zhan, Winghung Ki, Jiawei ZhengAbstract:A low-dropout regulator (LDR) using a matching-enhanced error amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation Capacitor or large ESR of the Output Capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2 of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.
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analysis and design of Output Capacitor free low dropout regulators with low quiescent current and high power supply rejection
IEEE Transactions on Circuits and Systems, 2014Co-Authors: Chenchang ZhanAbstract:This paper summarizes and extends our discussions on the recently developed Output-Capacitor-free low-dropout regulators (LDRs) with low quiescent current and high power supply rejection (LQC-HPSR LDRs) for SoC power management applications. By modifying the biasing scheme in a cascoding-based high-PSR topology, quiescent current consumption is significantly reduced while high PSR over a wide frequency range is maintained. The operation principle of the LQC-HPSR LDRs is elaborated and comprehensive analysis of PSR at different frequency ranges is presented. Furthermore, a novel implementation with enhanced robustness is proposed to limit the internal voltage range and accelerate the start-up speed as well. Two 12 mA LQC-HPSR LDRs-the first has one and the second has two NMOS transistors cascoded to the core regulator-have been designed in a 0.35- μm CMOS process with active areas of 0.055 mm2 and 0.084 mm2, respectively. Experimental results showed that they had dropout voltages of 0.4 V and 0.6 V, and achieved PSRs better than -23.0 dB and -38.0 dB up to 50 MHz at full load while consuming quiescent currents of only 28.6 μA and 43.9 μA, respectively.
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an Output Capacitor free adaptively biased low dropout regulator with subthreshold undershoot reduction for soc
IEEE Transactions on Circuits and Systems, 2012Co-Authors: Chenchang ZhanAbstract:This paper presents an Output-Capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of adaptive biasing (AB) and Miller compensation with Q-reduction are employed to achieve low-voltage high-precision regulation with extended loop bandwidth while maintaining low quiescent current and high current efficiency. The pass transistor is designed to work in the linear region at heavy load to save silicon area, and a symmetrically matched current-voltage mirror is used to implement the AB scheme with accurate current sensing for the full load range. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily but exponentially increase the gate discharging current of the pass transistor when the LDR Output has a large undershoot due to a large step up of the load current. Undershoot voltage is hence dramatically reduced. Stability of the ABSTUR LDR is thoroughly analyzed and tradeoffs between the undershoot-reduction strength and the light load stability are discussed. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.
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Output Capacitor free adaptively biased low dropout regulator for system on chips
IEEE Transactions on Circuits and Systems, 2010Co-Authors: Chenchang Zhan, Winghung KiAbstract:A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage Output-Capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ?m CMOS technology ( Vtn ? 0.52 V and Vtp ? -0.72 V). The Output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ?A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low Output impedance.
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a high precision low voltage low dropout regulator for soc with adaptive biasing
International Symposium on Circuits and Systems, 2009Co-Authors: Chenchang ZhanAbstract:A high-precision low-voltage low dropout regulator (LDR) using adaptive biasing to extend the loop bandwidth is proposed for system-on-chip power management applications. The multi-stage Output-Capacitor-free LDR is stabilized by miller compensation and Q-reduction technique to reduce the requirement of minimum load current. By using direct current feedback from a simple current mirror, the adaptively-biased LDR achieves higher loop bandwidth, faster load and line transient responses, higher power supply rejection and lower Output impedance. The load and line regulations are also improved. Designed in a standard 0.35µm CMOS technology (V tn ≈ 0.52V and V tp ≈ −0.72V ), the 1.2V input 1.0V Output LDR requires a minimum load current of 50µA and delivers a maximum current of 100mA. Both theoretical analysis and simulation results are presented to demonstrate the advantages of the proposed LDR.
Yue Wang - One of the best experts on this subject based on the ideXlab platform.
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stability analysis of digitally controlled dual active bridge converters
Journal of Modern Power Systems and Clean Energy, 2018Co-Authors: Ling Shi, Wanjun Lei, L I Zhuoqiang, Yao Cui, Jun Huang, Yue WangAbstract:The dual active bridge (DAB) converters are widely used in the energy storage equipment and the distributed power systems. However, the existence of switching nonlinearity and control delay can cause serious stability problem to the DAB converters. Thus, this paper, studies the stability of a digitally controlled DAB converter with an Output voltage closed loop controller. Firstly, to accurately study the stability in a DAB converter, a discrete-time model established in a whole switching period is obtained. The model considers the Output Capacitor ESR, the digital control delay, and sample-and-hold process. By using this model, the stabilities of the DAB converter versus the proportional controller parameter and the Output Capacitor ESR are analyzed and the critical values are predicted accurately. Moreover, the stability boundary of the proportional controller parameter and the Output Capacitor ESR is also obtained. The result shows that the value of the Output Capacitor ESR can have a great effect on the stability region of the proportional controller parameter. Finally, the theoretical analyses are verified by the simulation and experimental results.
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bilinear discrete time modeling and stability analysis of the digitally controlled dual active bridge converter
IEEE Transactions on Power Electronics, 2017Co-Authors: Ling Shi, Wanjun Lei, Yao Cui, Jun Huang, Yue WangAbstract:Dual active bridge (DAB) converters have been widely used in distributed power systems and energy storage equipment. However, the inherent nonlinearity of the DAB converters can cause stability problem, such as Output voltage oscillation. In this paper, the dynamic behavior and stability of a digitally controlled DAB converter with a closed-loop controller are studied. First, to accurately study the nonlinear dynamics and stability in a DAB converter, a bilinear discrete-time model considering the Output Capacitor equivalent series resistance (ESR) and the digital control delay in circuit is established. Based on the model, the nonlinear dynamic characteristic and stability of the DAB converter versus the control parameter are studied. Furthermore, extensive analyses are performed to study the effect of the transformer leakage inductance and the Output Capacitor ESR on the stability boundaries of the control parameter. The accuracy of the model and the theoretical analyses are validated by simulation and experimental results. The proposed model of the digitally controlled DAB converter can accurately predict the stability boundaries, which can be effectively applied to the design of the system parameters and guarantee stable operation of the converter.
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full discrete time modeling and stability analysis of the digital controlled dual active bridge converter
International Power Electronics and Motion Control Conference, 2016Co-Authors: Ling Shi, Wanjun Lei, Yao Cui, Jun Huang, Yue WangAbstract:The dual active bridge (DAB) converter has been widely used in the distributed power systems and the energy storage devices. However, the inherent nonlinearity of the DAB converter can cause serious stability problem. In this paper, the dynamics of a digital controlled DAB converter with Output voltage closed loop control is studied. Firstly, to accurately study the nonlinear dynamics and stability in a DAB converter, a full discrete-time model for the DAB converter is established. The model considers the ESR of the Output Capacitor and also considers the digital control delay and sample-and-hold process. Using this model, the stability of the DAB converter versus the parameter of the proportional controller is analyzed and the stability boundary is accurately predicted. Further, this paper also points out that the ESR of the Output Capacitor can bring a great effect to the stability of the system. Finally, simulation and experimental results verify the theoretical analysis.
Winghung Ki - One of the best experts on this subject based on the ideXlab platform.
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a 0 035mm2 150ma fast response low dropout regulator based on matching enhanced error amplifier and multi threshold controlled unity gain buffer in 0 13μm cmos
International Symposium on Circuits and Systems, 2016Co-Authors: Chenchang Zhan, Winghung Ki, Jiawei ZhengAbstract:A low-dropout regulator (LDR) using a matching-enhanced error amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation Capacitor or large ESR of the Output Capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2 of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.
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Output Capacitor free adaptively biased low dropout regulator for system on chips
IEEE Transactions on Circuits and Systems, 2010Co-Authors: Chenchang Zhan, Winghung KiAbstract:A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage Output-Capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ?m CMOS technology ( Vtn ? 0.52 V and Vtp ? -0.72 V). The Output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ?A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low Output impedance.
Ling Shi - One of the best experts on this subject based on the ideXlab platform.
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stability analysis of digitally controlled dual active bridge converters
Journal of Modern Power Systems and Clean Energy, 2018Co-Authors: Ling Shi, Wanjun Lei, L I Zhuoqiang, Yao Cui, Jun Huang, Yue WangAbstract:The dual active bridge (DAB) converters are widely used in the energy storage equipment and the distributed power systems. However, the existence of switching nonlinearity and control delay can cause serious stability problem to the DAB converters. Thus, this paper, studies the stability of a digitally controlled DAB converter with an Output voltage closed loop controller. Firstly, to accurately study the stability in a DAB converter, a discrete-time model established in a whole switching period is obtained. The model considers the Output Capacitor ESR, the digital control delay, and sample-and-hold process. By using this model, the stabilities of the DAB converter versus the proportional controller parameter and the Output Capacitor ESR are analyzed and the critical values are predicted accurately. Moreover, the stability boundary of the proportional controller parameter and the Output Capacitor ESR is also obtained. The result shows that the value of the Output Capacitor ESR can have a great effect on the stability region of the proportional controller parameter. Finally, the theoretical analyses are verified by the simulation and experimental results.
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bilinear discrete time modeling and stability analysis of the digitally controlled dual active bridge converter
IEEE Transactions on Power Electronics, 2017Co-Authors: Ling Shi, Wanjun Lei, Yao Cui, Jun Huang, Yue WangAbstract:Dual active bridge (DAB) converters have been widely used in distributed power systems and energy storage equipment. However, the inherent nonlinearity of the DAB converters can cause stability problem, such as Output voltage oscillation. In this paper, the dynamic behavior and stability of a digitally controlled DAB converter with a closed-loop controller are studied. First, to accurately study the nonlinear dynamics and stability in a DAB converter, a bilinear discrete-time model considering the Output Capacitor equivalent series resistance (ESR) and the digital control delay in circuit is established. Based on the model, the nonlinear dynamic characteristic and stability of the DAB converter versus the control parameter are studied. Furthermore, extensive analyses are performed to study the effect of the transformer leakage inductance and the Output Capacitor ESR on the stability boundaries of the control parameter. The accuracy of the model and the theoretical analyses are validated by simulation and experimental results. The proposed model of the digitally controlled DAB converter can accurately predict the stability boundaries, which can be effectively applied to the design of the system parameters and guarantee stable operation of the converter.
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full discrete time modeling and stability analysis of the digital controlled dual active bridge converter
International Power Electronics and Motion Control Conference, 2016Co-Authors: Ling Shi, Wanjun Lei, Yao Cui, Jun Huang, Yue WangAbstract:The dual active bridge (DAB) converter has been widely used in the distributed power systems and the energy storage devices. However, the inherent nonlinearity of the DAB converter can cause serious stability problem. In this paper, the dynamics of a digital controlled DAB converter with Output voltage closed loop control is studied. Firstly, to accurately study the nonlinear dynamics and stability in a DAB converter, a full discrete-time model for the DAB converter is established. The model considers the ESR of the Output Capacitor and also considers the digital control delay and sample-and-hold process. Using this model, the stability of the DAB converter versus the parameter of the proportional controller is analyzed and the stability boundary is accurately predicted. Further, this paper also points out that the ESR of the Output Capacitor can bring a great effect to the stability of the system. Finally, simulation and experimental results verify the theoretical analysis.
Guohua Zhou - One of the best experts on this subject based on the ideXlab platform.
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Asynchronous-Switching Map-Based Stability Effects of Circuit Parameters in Fixed Off-Time Controlled Buck Converter
IEEE Transactions on Power Electronics, 2016Co-Authors: Xi Zhang, Bocheng Bao, Jianping Xu, Guohua ZhouAbstract:Both constant on-time (COT) and fixed off-time (FOT) control techniques are suitable for various applications requiring fast transient response. However, the discrete-time model of COT controlled buck converter only has two switched borderlines, whereas that of FOT controlled buck converter has four switched borderlines. Based on the derivations of these borderlines, an asynchronous-switching map of FOT controlled buck converter is established. With the decrease of equivalent series resistance (ESR) of Output Capacitor, instability and mode shifting from continuous conduction mode (CCM) to discontinuous conduction mode (DCM) are discussed. Furthermore, with small ESR of Output Capacitor, stability effects of load resistance and inductance on dynamical behaviors are investigated, and the approximate stability criteria and the corresponding normalized critical conditions are obtained. The theoretical analyses and experimental results show that the converter operates in DCM chaos via period-doubling and border-collision bifurcation routes, and its instability caused by small ESR can be removed by choosing appropriate load resistance, inductance, and voltage transfer ratio, which are very suitable for the circuit design of FOT controlled buck converter.
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pulse train controlled ccm buck converter with small esr Output Capacitor
IEEE Transactions on Industrial Electronics, 2013Co-Authors: Jinping Wang, Jianping Xu, Guohua ZhouAbstract:The pulse-train (PT) control technique for switching dc-dc converters is simple to design and benefits from excellent control performance. Up to now, almost all of the works on PT control are focused on switching dc-dc converters operating in discontinuous conduction mode, with few works reported on PT control of switching dc-dc converters operating in continuous conduction mode (CCM). In this paper, a PT-controlled CCM buck converter is studied and a unique low-frequency oscillation phenomenon is revealed, which results in large undesired inductor-current and Output-voltage variations. The effect of equivalent series resistance (ESR) Output-Capacitor on the low-frequency oscillation is examined. The results indicate that such oscillation occurs when the ESR Output-Capacitor is relatively small and disappears when it is relatively large. However, a larger ESR will result in a large Output-voltage ripple. In order to avoid the low-frequency oscillation and, at the same time, to ensure a small Output-voltage ripple, the ICRIF circuit is applied. In this way, a small ESR Output-Capacitor can be used to decrease the Output-voltage ripple. Simulation and experimental results are provided to verify the theoretical analysis.
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Effect of Output Capacitor ESR on dynamic performance of voltage-mode hysteretic controlled buck converter
Electronics Letters, 2013Co-Authors: Jingyu Yang, Juan Xu, X. Zhang, Guohua ZhouAbstract:Different types of Capacitors have different parameters, e.g. equivalent series resistance (ESR) and capacitance. In switching DC-DC converters with voltage-mode (VM) hysteretic control, the Output Capacitor ESR has a significant effect on dynamic performance. In this reported work, two critical conditions of the Output Capacitor ESR for mode shifting and normal operation of the VM hysteretic controlled buck converter are derived. These results, verified by circuit simulations, illustrate that the larger Output Capacitor ESR is necessary for the converter operating normally; otherwise, the converter operates abnormally.
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dynamical effects of equivalent series resistance of Output Capacitor in constant on time controlled buck converter
IEEE Transactions on Industrial Electronics, 2013Co-Authors: Jinping Wang, Guohua Zhou, Jianping Xu, Wen HuAbstract:Equivalent series resistance (ESR) of Output Capacitor has a significant effect on the control performance of constant on-time (COT) controlled switching dc-dc converters. In this paper, a discrete-time model of COT-controlled buck converter, with variable sampling frequency, is established. Based upon which, the dynamical effects of the ESR of Output Capacitor on COT-controlled buck converter are revealed and analyzed. The time-domain numerical simulations of the exact switched state equations, the bifurcation diagrams, and maximal Lyapunov exponents of the discrete-time model are obtained. These results verified by experimental circuit indicate that the ESR of Output Capacitor is a critical factor for COT-controlled buck converter, which can eliminate the unique pulse bursting phenomenon and shift operation mode from discontinuous conduction mode to continuous conduction mode, as well as control stability.
