The Experts below are selected from a list of 20349 Experts worldwide ranked by ideXlab platform
Chi Sing Leung - One of the best experts on this subject based on the ideXlab platform.
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On Wang $k$ WTA With Input Noise, Output Node Stochastic, and Recurrent State Noise
IEEE Transactions on Neural Networks and Learning Systems, 2018Co-Authors: Chi Sing Leung, Kevin I.-j. HoAbstract:In this paper, the effect of input noise, Output Node stochastic, and recurrent state noise on the Wang kWTA is analyzed. Here, we assume that noise exists at the recurrent state y(t) and it can either be additive or multiplicative. Besides, its dynamical change (i.e., dy/dt) is corrupted by noise as well. In sequel, we model the dynamics of y(t) as a stochastic differential equation and show that the stochastic behavior of y(t) is equivalent to an Ito diffusion. Its stationary distribution is a Gibbs distribution, whose modality depends on the noise condition. With moderate input noise and very small recurrent state noise, the distribution is single modal and hence y(∞) has high probability varying within the input values of the k and k + 1 winners (i.e., correct Output). With small input noise and large recurrent state noise, the distribution could be multimodal and hence y(∞) could have probability varying outside the input values of the k and k + 1 winners (i.e., incorrect Output). In this regard, we further derive the conditions that the kWTA has high probability giving correct Output. Our results reveal that recurrent state noise could have severe effect on Wang kWTA. But, input noise and Output Node stochastic could alleviate such an effect.
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Effect of Input Noise and Output Node Stochastic on Wang's k WTA
IEEE Transactions on Neural Networks and Learning Systems, 2013Co-Authors: Chi Sing Leung, Kevin HoAbstract:Recently, an analog neural network model, namely Wang's kWTA, was proposed. In this model, the Output Nodes are defined as the Heaviside function. Subsequently, its finite time convergence property and the exact convergence time are analyzed. However, the discovered characteristics of this model are based on the assumption that there are no physical defects during the operation. In this brief, we analyze the convergence behavior of the Wang's kWTA model when defects exist during the operation. Two defect conditions are considered. The first one is that there is input noise. The second one is that there is stochastic behavior in the Output Nodes. The convergence of the Wang's kWTA under these two defects is analyzed and the corresponding energy function is revealed.
Eduard Alarcon - One of the best experts on this subject based on the ideXlab platform.
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high slew rate current mode transconductance error amplifier for low quiescent current Output capacitorless cmos ldo regulator
Integration, 2014Co-Authors: Rasoul Fathipour, Alireza Saberkari, Herminio Martinez, Eduard AlarconAbstract:This paper presents a CMOS low quiescent current Output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18@?m CMOS process to supply the load current between 0 and 100mA. The dropout voltage of the LDO is set to 200mV for 1.2-2V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip Output capacitor or lumped parasitic capacitances at the Output Node between 10 and 100pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7@?A. A final benchmark comparison considering all relevant performance metrics is presented.
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Output capacitorless cmos ldo regulator based on high slew rate current mode transconductance amplifier
International Symposium on Circuits and Systems, 2013Co-Authors: Alireza Saberkari, Rasoul Fathipour, Herminio Martinez, A Poveda, Eduard AlarconAbstract:A low quiescent current Output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip Output capacitor or lumped parasitic capacitances at the Output Node between 10-100 pF.
Kevin I.-j. Ho - One of the best experts on this subject based on the ideXlab platform.
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On Wang $k$ WTA With Input Noise, Output Node Stochastic, and Recurrent State Noise
IEEE Transactions on Neural Networks and Learning Systems, 2018Co-Authors: Chi Sing Leung, Kevin I.-j. HoAbstract:In this paper, the effect of input noise, Output Node stochastic, and recurrent state noise on the Wang kWTA is analyzed. Here, we assume that noise exists at the recurrent state y(t) and it can either be additive or multiplicative. Besides, its dynamical change (i.e., dy/dt) is corrupted by noise as well. In sequel, we model the dynamics of y(t) as a stochastic differential equation and show that the stochastic behavior of y(t) is equivalent to an Ito diffusion. Its stationary distribution is a Gibbs distribution, whose modality depends on the noise condition. With moderate input noise and very small recurrent state noise, the distribution is single modal and hence y(∞) has high probability varying within the input values of the k and k + 1 winners (i.e., correct Output). With small input noise and large recurrent state noise, the distribution could be multimodal and hence y(∞) could have probability varying outside the input values of the k and k + 1 winners (i.e., incorrect Output). In this regard, we further derive the conditions that the kWTA has high probability giving correct Output. Our results reveal that recurrent state noise could have severe effect on Wang kWTA. But, input noise and Output Node stochastic could alleviate such an effect.
Kevin Ho - One of the best experts on this subject based on the ideXlab platform.
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Effect of Input Noise and Output Node Stochastic on Wang's k WTA
IEEE Transactions on Neural Networks and Learning Systems, 2013Co-Authors: Chi Sing Leung, Kevin HoAbstract:Recently, an analog neural network model, namely Wang's kWTA, was proposed. In this model, the Output Nodes are defined as the Heaviside function. Subsequently, its finite time convergence property and the exact convergence time are analyzed. However, the discovered characteristics of this model are based on the assumption that there are no physical defects during the operation. In this brief, we analyze the convergence behavior of the Wang's kWTA model when defects exist during the operation. Two defect conditions are considered. The first one is that there is input noise. The second one is that there is stochastic behavior in the Output Nodes. The convergence of the Wang's kWTA under these two defects is analyzed and the corresponding energy function is revealed.
Ken Choi - One of the best experts on this subject based on the ideXlab platform.
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high performance low cost and robust soft error tolerant latch designs for nanoscale cmos technology
IEEE Transactions on Circuits and Systems, 2012Co-Authors: Haiqing Nan, Ken ChoiAbstract:In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are completely insensitive to transient faults at their internal Nodes and Output Node independent of the size and technology of the CMOS transistor. The proposed latches tolerate transient faults regardless of the energy of the striking particle. The proposed latches offer faster speed, higher reliability to transient faults with lower costs regarding power and area than most of the latches recently proposed in the literature. The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch.