The Experts below are selected from a list of 4008 Experts worldwide ranked by ideXlab platform
Ebrahim Babaei - One of the best experts on this subject based on the ideXlab platform.
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Interleaved Buck–Boost N-Phase High-Efficiency Converter with Soft Switching and Low Output Voltage Ripple
Arabian Journal for Science and Engineering, 2021Co-Authors: Ahwan Rahimi, Vida Ranjbarizad, Ebrahim BabaeiAbstract:In this paper, an interleaved buck–boost n-phase converter with the soft-switching operation is proposed. All the switches are switched at zero Voltage by applying an inductor between every two consecutive phases. These inductors cause the soft-switching operation through all switches of the converter by discharging the inherent Voltage of switches’ capacitor and keeping the Voltage of switch at zero until the switching period ends. Also, due to the existence of these inductors, the Output diodes are disconnected during zero current. The large number of phases in this kind of converter reduces the Output Voltage Ripple, Output and input current Ripple and increases the reliability of the converter. Increasing the number of phases of the converter reduces the current stress on the power switches and, thereby, leads to reducing conduction losses of the power switches. This kind of converter has a high efficiency due to its soft-switching operation of switches and reduction of the conduction losses of all switches. Finally, the experimental results of a four-phase prototype of this converter with 100 W Output power for input Voltage 20 V and Output Voltage 100 V are presented for determining the features of the desired converter.
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performance analysis and calculation of critical inductance and Output Voltage Ripple of a simple non isolated multi input bidirectional dc dc converter
International Journal of Circuit Theory and Applications, 2018Co-Authors: Kazem Varesi, Ebrahim Babaei, Mehran Sabahi, Seyed Hossein HosseiniAbstract:Summary In this paper, a simple non-isolated multiple input (MI) bidirectional DC-DC topology is proposed which can operate in buck, boost, or buck-boost modes. The proposed topology utilizes a battery pack to realize the bidirectional power flow operation especially when the input sources are non-storable ones. The excess energy of input sources can be stored in the battery and be injected to the load, when required. Simultaneous or independent power transfer of input sources is also provided. For better evaluation, the proposed topology has been compared with several recently presented novel topologies, from view point of number of inductors, capacitors, switches, and diodes. Comparison results show that the proposed topology utilizes less number of components (switches, inductors, capacitors, and current sensors) which can reduce the size, cost, and complexity of converter. Different operational modes of the proposed topology (unidirectional buck, boost, buck-boost modes, and bidirectional mode) have been presented. Also, boost mode of the proposed topology has been investigated in detail, from design point of view, and generalized relationships have been proposed for calculation of critical inductance (CI) and Output Voltage Ripple (OVR) of proposed n-input boost topology. To validate proposed theoretical concepts, the proposed topology has been modeled and simulated in PSCAD/EMTDC software, and the 3-input boost version has been experimentally implemented. Simulation and experimental results confirm appropriate performance of the proposed topology.
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Performance analysis and calculation of critical inductance and Output Voltage Ripple of a simple non‐isolated multi‐input bidirectional DC‐DC converter
International Journal of Circuit Theory and Applications, 2017Co-Authors: Kazem Varesi, Seyed Hossein Hosseini, Mehran Sabahi, Ebrahim BabaeiAbstract:Summary In this paper, a simple non-isolated multiple input (MI) bidirectional DC-DC topology is proposed which can operate in buck, boost, or buck-boost modes. The proposed topology utilizes a battery pack to realize the bidirectional power flow operation especially when the input sources are non-storable ones. The excess energy of input sources can be stored in the battery and be injected to the load, when required. Simultaneous or independent power transfer of input sources is also provided. For better evaluation, the proposed topology has been compared with several recently presented novel topologies, from view point of number of inductors, capacitors, switches, and diodes. Comparison results show that the proposed topology utilizes less number of components (switches, inductors, capacitors, and current sensors) which can reduce the size, cost, and complexity of converter. Different operational modes of the proposed topology (unidirectional buck, boost, buck-boost modes, and bidirectional mode) have been presented. Also, boost mode of the proposed topology has been investigated in detail, from design point of view, and generalized relationships have been proposed for calculation of critical inductance (CI) and Output Voltage Ripple (OVR) of proposed n-input boost topology. To validate proposed theoretical concepts, the proposed topology has been modeled and simulated in PSCAD/EMTDC software, and the 3-input boost version has been experimentally implemented. Simulation and experimental results confirm appropriate performance of the proposed topology.
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high step up dc dc converter with minimum Output Voltage Ripple
IEEE Transactions on Industrial Electronics, 2017Co-Authors: Hamed Mashinchi Maheri, Ebrahim Babaei, Mehran Sabahi, Seyed Hossein HosseiniAbstract:In this paper, a new structure for high step-up dc–dc converters is proposed. In the proposed structure, it is possible to extend the topology by increasing the number of active–passive inductor cells. High Voltage gain with lower duty cycle, low-current and -Voltage stresses on switches, small inductors, and small size of filter are the main advantages of the proposed structure. The proposed converter is analyzed in different operating modes. In order to design the components’ values of the proposed converter, the equations of Output Voltage Ripple are calculated in each operating mode and a design procedure is proposed based on the aforementioned equations. Moreover, the losses and efficiency of the converter are calculated. In order to validate the correctness of calculations and analyses, the experimental results are given.
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Calculation of Output Voltage Ripple and Design Considerations of SEPIC Converter
IEEE Transactions on Industrial Electronics, 2014Co-Authors: Ebrahim Babaei, Mir Esmaeel Seyed MahmoodiehAbstract:In this paper, a design method is proposed for finding the equivalent inductance and capacitance of the single-ended primary-inductor converter (SEPIC). The relations of the Output Voltage Ripple (OVR) of the SEPIC converter are obtained in complete inductor supply mode-continuous conduction mode (CISM-CCM), incomplete inductor supply mode-CCM (IISM-CCM), and IISM-discontinuous conduction mode (IISM-DCM). The maximum of OVR (MOVR) is investigated for a specified range of the input Voltage and load resistance. This value of the MOVR is obtained for the minimum values of input Voltage and load resistance. In this paper, the minimum values of the equivalent inductance and capacitance are calculated in obtaining the minimum value of the MOVR. One of the other performed studies in this paper is calculation of the switch peak current in CCM and DCM. In addition, the converter is designed based on the minimum values of the MOVR and stress of the switching current. Experimental and simulation results are used to prove the validity of the presented theoretical subjects.
Ying-hsi Lin - One of the best experts on this subject based on the ideXlab platform.
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a right half plane zero free buck boost dc dc converter with 97 46 high efficiency and low Output Voltage Ripple
Symposium on VLSI Circuits, 2019Co-Authors: Yenan Lin, Ke-horng Chen, Ying-hsi Lin, Tzuping Huang, Youzheng Ouyang, Minghsien Lin, Hungting ChouAbstract:The right-half-plane (RHP) zero can be eliminated in the proposed buck-boost (BB) converter to achieve fast transients for Internet-of-Thing (IoT) applications. The pseudo-boost mode in the BB converter eliminates one power switch in the current path and ensures that the continuous inductor current is half of the conventional design value to achieve 97.46% peak efficiency. Besides, the Output Voltage Ripple is reduced to 7mV. By inserting an additional phase, a smooth transition between the buck and pseudo-boost modes ensures a Voltage drop less than 15mV. The slope-based transient enhancement (SBTE) circuit accelerates transient response in 9 $\mu$S with a load variation of 400 mA.
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VLSI Circuits - A Right-Half-Plane Zero-Free Buck-Boost DC-DC Converter with 97.46% High Efficiency and Low Output Voltage Ripple
2019 Symposium on VLSI Circuits, 2019Co-Authors: Yenan Lin, Ke-horng Chen, Ying-hsi Lin, Tzuping Huang, Minghsien Lin, You-zheng Ou-yang, Hungting ChouAbstract:The right-half-plane (RHP) zero can be eliminated in the proposed buck-boost (BB) converter to achieve fast transients for Internet-of-Thing (IoT) applications. The pseudo-boost mode in the BB converter eliminates one power switch in the current path and ensures that the continuous inductor current is half of the conventional design value to achieve 97.46% peak efficiency. Besides, the Output Voltage Ripple is reduced to 7mV. By inserting an additional phase, a smooth transition between the buck and pseudo-boost modes ensures a Voltage drop less than 15mV. The slope-based transient enhancement (SBTE) circuit accelerates transient response in 9 $\mu$S with a load variation of 400 mA.
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ESSCIRC - A Pseudo-Ramp Controlled Three Level Buck Converter with an Auto-Ripple Cancellation Technique for Low Output Voltage Ripple in Sub-Threshold Applications
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018Co-Authors: Li-cheng Chu, Shao-qi Chen, Ke-horng Chen, Ying-hsi Lin, Shian-ru Lin, Tsung-yen TsaiAbstract:In high switching frequency and low duty conversion, the on-time in duty cycle is restrained to brief period. The three-level converter extends the on-time to two times larger. By Pseudo-Ramp Controller (PRC) and Auto-Ripple Cancellation (ARC) Topology, flying capacitors are balanced to 50% input Voltage with the accuracy of duty cycle improves 11 times and 3mV Output Voltage Ripple.
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A-SSCC - Ultra-low Voltage Ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016Co-Authors: Chen-fan Tang, Ke-horng Chen, Ying-hsi Lin, Chin-long Wey, Jian-ru Lin, Tsung-yen TsaiAbstract:Overall consideration including bonding wire effects is needed because conventional DC-DC boost converter used in energy harvesting systems suffers from large Output Voltage Ripple in steady state and transient response. Thus, this paper proposed the pumping capacitor and wire inductance (PCWI) technique to suppress Output Voltage Ripple to an ultra-low value. Small steady state Voltage across the wire inductance (WI) and continuous WI current can be ensured by an additional pumping capacitor (PC). Moreover, even in case of an ultra-low Output Voltage Ripple, the proposed pseudo-inductor current (PIC) technique regenerates the inductor current information to eliminate the instability problem in conventional Ripple-based control techniques. Transient recovery time and Output Voltage variation can be reduced simultaneously. Test chip was fabricated in 0.18-μm 5V/24V CMOS process when input Voltage of 1.8–5.5V is converted to 12.8V. Experimental results show the ratio of Output Voltage Ripple and Output Voltage is reduced to 0.04%. Measured power conversion efficiency is around 92% at 100mA and 96% at 0.1mA.
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Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter
IEEE Journal of Solid-State Circuits, 2011Co-Authors: Yu-huei Lee, Ke-horng Chen, Tzu-chi Huang, Yao-yi Yang, Wen-shen Chou, Chen-chih Huang, Ying-hsi LinAbstract:A single-inductor dual-Output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-Voltage energy distribution controller (LV-EDC) can simultaneously guarantee good Voltage regulation and low Output Voltage Ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state Output Voltage Ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual Outputs. Moreover, within the allowable Output Voltage Ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring Voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm2 and achieves 91% peak efficiency, low Output Voltage Ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
Ke-horng Chen - One of the best experts on this subject based on the ideXlab platform.
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a right half plane zero free buck boost dc dc converter with 97 46 high efficiency and low Output Voltage Ripple
Symposium on VLSI Circuits, 2019Co-Authors: Yenan Lin, Ke-horng Chen, Ying-hsi Lin, Tzuping Huang, Youzheng Ouyang, Minghsien Lin, Hungting ChouAbstract:The right-half-plane (RHP) zero can be eliminated in the proposed buck-boost (BB) converter to achieve fast transients for Internet-of-Thing (IoT) applications. The pseudo-boost mode in the BB converter eliminates one power switch in the current path and ensures that the continuous inductor current is half of the conventional design value to achieve 97.46% peak efficiency. Besides, the Output Voltage Ripple is reduced to 7mV. By inserting an additional phase, a smooth transition between the buck and pseudo-boost modes ensures a Voltage drop less than 15mV. The slope-based transient enhancement (SBTE) circuit accelerates transient response in 9 $\mu$S with a load variation of 400 mA.
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VLSI Circuits - A Right-Half-Plane Zero-Free Buck-Boost DC-DC Converter with 97.46% High Efficiency and Low Output Voltage Ripple
2019 Symposium on VLSI Circuits, 2019Co-Authors: Yenan Lin, Ke-horng Chen, Ying-hsi Lin, Tzuping Huang, Minghsien Lin, You-zheng Ou-yang, Hungting ChouAbstract:The right-half-plane (RHP) zero can be eliminated in the proposed buck-boost (BB) converter to achieve fast transients for Internet-of-Thing (IoT) applications. The pseudo-boost mode in the BB converter eliminates one power switch in the current path and ensures that the continuous inductor current is half of the conventional design value to achieve 97.46% peak efficiency. Besides, the Output Voltage Ripple is reduced to 7mV. By inserting an additional phase, a smooth transition between the buck and pseudo-boost modes ensures a Voltage drop less than 15mV. The slope-based transient enhancement (SBTE) circuit accelerates transient response in 9 $\mu$S with a load variation of 400 mA.
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ESSCIRC - A Pseudo-Ramp Controlled Three Level Buck Converter with an Auto-Ripple Cancellation Technique for Low Output Voltage Ripple in Sub-Threshold Applications
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018Co-Authors: Li-cheng Chu, Shao-qi Chen, Ke-horng Chen, Ying-hsi Lin, Shian-ru Lin, Tsung-yen TsaiAbstract:In high switching frequency and low duty conversion, the on-time in duty cycle is restrained to brief period. The three-level converter extends the on-time to two times larger. By Pseudo-Ramp Controller (PRC) and Auto-Ripple Cancellation (ARC) Topology, flying capacitors are balanced to 50% input Voltage with the accuracy of duty cycle improves 11 times and 3mV Output Voltage Ripple.
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A-SSCC - Ultra-low Voltage Ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016Co-Authors: Chen-fan Tang, Ke-horng Chen, Ying-hsi Lin, Chin-long Wey, Jian-ru Lin, Tsung-yen TsaiAbstract:Overall consideration including bonding wire effects is needed because conventional DC-DC boost converter used in energy harvesting systems suffers from large Output Voltage Ripple in steady state and transient response. Thus, this paper proposed the pumping capacitor and wire inductance (PCWI) technique to suppress Output Voltage Ripple to an ultra-low value. Small steady state Voltage across the wire inductance (WI) and continuous WI current can be ensured by an additional pumping capacitor (PC). Moreover, even in case of an ultra-low Output Voltage Ripple, the proposed pseudo-inductor current (PIC) technique regenerates the inductor current information to eliminate the instability problem in conventional Ripple-based control techniques. Transient recovery time and Output Voltage variation can be reduced simultaneously. Test chip was fabricated in 0.18-μm 5V/24V CMOS process when input Voltage of 1.8–5.5V is converted to 12.8V. Experimental results show the ratio of Output Voltage Ripple and Output Voltage is reduced to 0.04%. Measured power conversion efficiency is around 92% at 100mA and 96% at 0.1mA.
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Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter
IEEE Journal of Solid-State Circuits, 2011Co-Authors: Yu-huei Lee, Ke-horng Chen, Tzu-chi Huang, Yao-yi Yang, Wen-shen Chou, Chen-chih Huang, Ying-hsi LinAbstract:A single-inductor dual-Output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-Voltage energy distribution controller (LV-EDC) can simultaneously guarantee good Voltage regulation and low Output Voltage Ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state Output Voltage Ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual Outputs. Moreover, within the allowable Output Voltage Ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring Voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm2 and achieves 91% peak efficiency, low Output Voltage Ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
Jiahui Wu - One of the best experts on this subject based on the ideXlab platform.
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Evaluation and Suppression of a Low-Frequency Output Voltage Ripple of a Single-Stage AC–DC Converter Based on an Output Impedance Model
IEEE Transactions on Industrial Electronics, 2019Co-Authors: Jianping Xu, Ping Yang, Jiahui WuAbstract:A single-stage ac-dc converter with high power factor (PF) usually suffers from a significant Output Voltage Ripple at double line frequency. In order to suppress such low-frequency Output Voltage Ripple and maintain high PF, a series compensation circuit (SCC), which generates the same magnitude but 180° phase shifted low-frequency Voltage Ripple, is connected in series with the Output of a power factor correction (PFC) converter. In this paper, an Output impedance model of the SCC is established and the relationship between the Output impedance of the SCC and the low-frequency Output Voltage Ripple of an ac-dc converter is analyzed. Based on the proposed Output impedance model, a low-frequency Output Voltage Ripple can be evaluated. To further reduce the low-frequency Output Voltage Ripple, an Output impedance shaping method with a virtual impedance is presented. The implementation of the virtual impedance of the SCC with average current mode control is studied. A flyback PFC converter with a buck SCC is implemented for the study of the suppression of the low-frequency Output Voltage Ripple. A prototype is designed to verify the analysis results.
Wen-zhuang Jiang - One of the best experts on this subject based on the ideXlab platform.
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Soft Switching Converter with Output Voltage Ripple Minimized
International Review of Electrical Engineering (IREE), 2017Co-Authors: Kuo-ing Hwu, Yeu-torng Yau, Wen-zhuang JiangAbstract:In this study, a control technique combining the pulse amplitude modulation (PAM) and the pulse width modulation (PWM) is presented to minimize the Output Voltage Ripple of the proposed converter. The proposed converter is a two-stage structure. The first stage, used to adjust the input Voltage of the second stage, is an active clamp buck-boost converter, and the second stage, used to reduce the Output Voltage Ripple, is a two-phase interleaved buck converter with an active clamp based on only one resonant circuit. Furthermore, the Output Voltage Ripple can be cancelled when the two-phase interleaved buck converter operates under the condition of individual duty cycles of 50% with a phase shift of 180o. Moreover, both the first stage and second stage converters can achieve zero Voltage switching (ZVS). Therefore, compared with hard switching control, the efficiency can be improved. Above all, the number of phases can be extended. Finally, the operating principles and experimental results are provided to verify the performance of the proposed converter.
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Reduction of low-frequency Output Voltage Ripple for isolated high-power-factor AC–DC converter
International Journal of Electronics Letters, 2016Co-Authors: Wen-zhuang JiangAbstract:ABSTRACTIn the article, an isolated high-power-factor AC-DC converter, combining the buck-boost and flyback converters, is developed based on only one switch. With a suitable design of the Voltage across the Output capacitor of the buck-boost converter in the proposed circuit, the low-frequency Output Voltage Ripple can be reduced. Therefore, the proposed converter possesses a smaller low-frequency Output Voltage Ripple than the traditional AC–DC flyback converter does. In addition, the Voltage stress on the Output capacitor of the buck-boost converter in the proposed circuit can be varied by the turns ratio of the transformer so as to increase design elasticity. And, some experimental results are provided to verify the effectiveness of the proposed circuit.