The Experts below are selected from a list of 60 Experts worldwide ranked by ideXlab platform
Suhwan Kim - One of the best experts on this subject based on the ideXlab platform.
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a 2 1 gb s 12 channel transmitter with phase emphasis embedded serializer for 55 in uhd intra Panel Interface
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Jihwan Park, Joohyung Chae, Yongun Jeong, Jaewhan Lee, Suhwan KimAbstract:Phase and amplitude emphasis are combined in a 2.1-Gb/s 12-channel transmitter for ultra-high definition (UHD) intra-Panel Interface. The transmitter performs phase emphasis within the final 2:1 stage of its 20:1 serializer. This reduces data-dependent jitter (DDJ) without increasing IO capacitance by making the timing of bit transitions depend on the previous data. We have also proved the compensation effect of this emphasis by a mathematical analysis. The low-voltage differential signaling (LVDS) driver in the transmitter can accommodate a 300-mV variation in common-mode voltage and swings of 300 mV–1.2 V in the output signal, so as to match the variations between channel characteristics which occur in large displays. A prototype was fabricated in 28-nm CMOS, and occupies 1.35 mm2; it was tested on a 55-in $3840 \times 2160$ thin-film transistor liquid-crystal display (TFT-LCD) intra-Panel Interface, where it compensated for channel losses exceeding 10 dB, while reducing eye jitter by 38%: phase emphasis is responsible for about half of this reduction.
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a 3 2 gb s 16 channel transmitter for intra Panel Interfaces with independently controllable output swing common mode voltage and equalization
IEEE Access, 2018Co-Authors: Joohyung Chae, Jihwan Park, Mino Kim, Gimoon Hong, Suhwan KimAbstract:The use of coupled-bias common-mode feedback allows a low-voltage differential signaling driver, implemented in a deep-submicron process, to adjust its output common-mode voltage, as well as the output swing and equalization strength independently. This form of differential signaling driver has been incorporated in a 16-channel transmitter for the timing controller of an intra-Panel Interface. The flexibility of its output characteristics allows it to accommodate the range of channel characteristics commonly found in the intra-Panel Interface of an ultra-high-definition display. Fabricated in a 28-nm bulk CMOS process, our 16-channel transmitter occupies 1.39 mm2. Its total power consumption is 203.2 mW with a supply voltage of 1.05 V, running at 3.2 Gb/s with the maximum output swing. Measurements confirm that the transmitter can operate from 0.8 to 3.2 Gb/s with channels that replicate those encountered in an intra-Panel Interface. The maximum controllable range of the output swing, the output common-mode voltage, and equalization are 216–1072 mVdiff, 291–604 mV, and 0–14.6 dB, respectively.
Leesup Kim - One of the best experts on this subject based on the ideXlab platform.
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an input data and power noise inducing clock jitter tolerant reference less digital cdr for lcd intra Panel Interface
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: Yonghun Kim, Hyunkyu Jeon, Taeho Lee, Dongil Lee, Leesup KimAbstract:This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-Panel Interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively.
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an intra Panel Interface with clock embedded differential signaling for tft lcd systems
IEEE\ OSA Journal of Display Technology, 2011Co-Authors: Hyunkyu Jeon, Y H Moon, Jinku Kang, Leesup KimAbstract:In this paper, an intra-Panel Interface with a clock embedded differential signaling for TFT-LCD systems is proposed. The proposed Interface reduces the number of signal lines between the timing controller and the column drivers in a TFT-LCD Panel by adopting the embedded clock scheme. The protocol of the proposed Interface provides a delay-locked loop (DLL)-based clock recovery scheme for the receiver. The timing controller and the column driver integrated with the proposed Interface are fabricated in 0.13- μm CMOS process technology and 0.18-μm high voltage CMOS process technology, respectively. The proposed Interface is verified on a 47-inch Full High-Definition (FHD) (1920RGBt1080) TFT-LCD Panel with 8-bit RGB and 120-Hz driving technology. The maximum data rate per differential pair was measured to be as high as 2.0 Gb/s in a wafer test.
Jihwan Park - One of the best experts on this subject based on the ideXlab platform.
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a 2 1 gb s 12 channel transmitter with phase emphasis embedded serializer for 55 in uhd intra Panel Interface
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Jihwan Park, Joohyung Chae, Yongun Jeong, Jaewhan Lee, Suhwan KimAbstract:Phase and amplitude emphasis are combined in a 2.1-Gb/s 12-channel transmitter for ultra-high definition (UHD) intra-Panel Interface. The transmitter performs phase emphasis within the final 2:1 stage of its 20:1 serializer. This reduces data-dependent jitter (DDJ) without increasing IO capacitance by making the timing of bit transitions depend on the previous data. We have also proved the compensation effect of this emphasis by a mathematical analysis. The low-voltage differential signaling (LVDS) driver in the transmitter can accommodate a 300-mV variation in common-mode voltage and swings of 300 mV–1.2 V in the output signal, so as to match the variations between channel characteristics which occur in large displays. A prototype was fabricated in 28-nm CMOS, and occupies 1.35 mm2; it was tested on a 55-in $3840 \times 2160$ thin-film transistor liquid-crystal display (TFT-LCD) intra-Panel Interface, where it compensated for channel losses exceeding 10 dB, while reducing eye jitter by 38%: phase emphasis is responsible for about half of this reduction.
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a 3 2 gb s 16 channel transmitter for intra Panel Interfaces with independently controllable output swing common mode voltage and equalization
IEEE Access, 2018Co-Authors: Joohyung Chae, Jihwan Park, Mino Kim, Gimoon Hong, Suhwan KimAbstract:The use of coupled-bias common-mode feedback allows a low-voltage differential signaling driver, implemented in a deep-submicron process, to adjust its output common-mode voltage, as well as the output swing and equalization strength independently. This form of differential signaling driver has been incorporated in a 16-channel transmitter for the timing controller of an intra-Panel Interface. The flexibility of its output characteristics allows it to accommodate the range of channel characteristics commonly found in the intra-Panel Interface of an ultra-high-definition display. Fabricated in a 28-nm bulk CMOS process, our 16-channel transmitter occupies 1.39 mm2. Its total power consumption is 203.2 mW with a supply voltage of 1.05 V, running at 3.2 Gb/s with the maximum output swing. Measurements confirm that the transmitter can operate from 0.8 to 3.2 Gb/s with channels that replicate those encountered in an intra-Panel Interface. The maximum controllable range of the output swing, the output common-mode voltage, and equalization are 216–1072 mVdiff, 291–604 mV, and 0–14.6 dB, respectively.
Joohyung Chae - One of the best experts on this subject based on the ideXlab platform.
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a 2 1 gb s 12 channel transmitter with phase emphasis embedded serializer for 55 in uhd intra Panel Interface
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Jihwan Park, Joohyung Chae, Yongun Jeong, Jaewhan Lee, Suhwan KimAbstract:Phase and amplitude emphasis are combined in a 2.1-Gb/s 12-channel transmitter for ultra-high definition (UHD) intra-Panel Interface. The transmitter performs phase emphasis within the final 2:1 stage of its 20:1 serializer. This reduces data-dependent jitter (DDJ) without increasing IO capacitance by making the timing of bit transitions depend on the previous data. We have also proved the compensation effect of this emphasis by a mathematical analysis. The low-voltage differential signaling (LVDS) driver in the transmitter can accommodate a 300-mV variation in common-mode voltage and swings of 300 mV–1.2 V in the output signal, so as to match the variations between channel characteristics which occur in large displays. A prototype was fabricated in 28-nm CMOS, and occupies 1.35 mm2; it was tested on a 55-in $3840 \times 2160$ thin-film transistor liquid-crystal display (TFT-LCD) intra-Panel Interface, where it compensated for channel losses exceeding 10 dB, while reducing eye jitter by 38%: phase emphasis is responsible for about half of this reduction.
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a 3 2 gb s 16 channel transmitter for intra Panel Interfaces with independently controllable output swing common mode voltage and equalization
IEEE Access, 2018Co-Authors: Joohyung Chae, Jihwan Park, Mino Kim, Gimoon Hong, Suhwan KimAbstract:The use of coupled-bias common-mode feedback allows a low-voltage differential signaling driver, implemented in a deep-submicron process, to adjust its output common-mode voltage, as well as the output swing and equalization strength independently. This form of differential signaling driver has been incorporated in a 16-channel transmitter for the timing controller of an intra-Panel Interface. The flexibility of its output characteristics allows it to accommodate the range of channel characteristics commonly found in the intra-Panel Interface of an ultra-high-definition display. Fabricated in a 28-nm bulk CMOS process, our 16-channel transmitter occupies 1.39 mm2. Its total power consumption is 203.2 mW with a supply voltage of 1.05 V, running at 3.2 Gb/s with the maximum output swing. Measurements confirm that the transmitter can operate from 0.8 to 3.2 Gb/s with channels that replicate those encountered in an intra-Panel Interface. The maximum controllable range of the output swing, the output common-mode voltage, and equalization are 216–1072 mVdiff, 291–604 mV, and 0–14.6 dB, respectively.
Hyunkyu Jeon - One of the best experts on this subject based on the ideXlab platform.
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an input data and power noise inducing clock jitter tolerant reference less digital cdr for lcd intra Panel Interface
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: Yonghun Kim, Hyunkyu Jeon, Taeho Lee, Dongil Lee, Leesup KimAbstract:This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-Panel Interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively.
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an intra Panel Interface with clock embedded differential signaling for tft lcd systems
IEEE\ OSA Journal of Display Technology, 2011Co-Authors: Hyunkyu Jeon, Y H Moon, Jinku Kang, Leesup KimAbstract:In this paper, an intra-Panel Interface with a clock embedded differential signaling for TFT-LCD systems is proposed. The proposed Interface reduces the number of signal lines between the timing controller and the column drivers in a TFT-LCD Panel by adopting the embedded clock scheme. The protocol of the proposed Interface provides a delay-locked loop (DLL)-based clock recovery scheme for the receiver. The timing controller and the column driver integrated with the proposed Interface are fabricated in 0.13- μm CMOS process technology and 0.18-μm high voltage CMOS process technology, respectively. The proposed Interface is verified on a 47-inch Full High-Definition (FHD) (1920RGBt1080) TFT-LCD Panel with 8-bit RGB and 120-Hz driving technology. The maximum data rate per differential pair was measured to be as high as 2.0 Gb/s in a wafer test.
