The Experts below are selected from a list of 102984 Experts worldwide ranked by ideXlab platform
Gabriel H Loh - One of the best experts on this subject based on the ideXlab platform.
-
efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
-
invited efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
S Q Zheng - One of the best experts on this subject based on the ideXlab platform.
-
fast and processor efficient Parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system
IEEE Transactions on Parallel and Distributed Systems, 1998Co-Authors: Keqin Li, S Q ZhengAbstract:We present efficient Parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of Parallel Communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support Parallel implementations of divide-and-conquer computations like Strassen's algorithm. The main contributions of the paper are as follows. We develop five matrix multiplication algorithms with varying degrees of Parallelism on the LARPBS computing model; namely, MM/sub 1/, MM/sub 2/, MM/sub 3/, and compound algorithms C/sub 1/(/spl epsiv/)and C/sub 2/(/spl delta/). Algorithm C/sub 1/(/spl epsiv/) has adjustable time complexity in sublinear level. Algorithm C/sub 2/(/spl delta/) implies that it is feasible to achieve sublogarithmic time using /spl sigma/(N/sup 3/) processors for matrix multiplication on a realistic system. Algorithms MM/sub 3/, C/sub 1/(/spl epsiv/), and C/sub 2/(/spl delta/) all have o(/spl Nscr//sup 3/) cost and, hence, are very processor efficient. Algorithms MM/sub 1/, MM/sub 3/, and C/sub 1/(/spl epsiv/) are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM/sub 2/ and C/sub 2/(/spl delta/) are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM/sub 2/ and C/sub 2/(/spl delta/) to unbounded integers and reals are also discussed.
-
fast and processor efficient Parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system
IEEE Transactions on Parallel and Distributed Systems, 1998Co-Authors: Yi Pan, S Q ZhengAbstract:We present efficient Parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of Parallel Communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support Parallel implementations of divide-and-conquer computations like Strassen's algorithm. The main contributions of the paper are as follows. We develop five matrix multiplication algorithms with varying degrees of Parallelism on the LARPBS computing model; namely, MM/sub 1/, MM/sub 2/, MM/sub 3/, and compound algorithms C/sub 1/(/spl epsiv/)and C/sub 2/(/spl delta/). Algorithm C/sub 1/(/spl epsiv/) has adjustable time complexity in sublinear level. Algorithm C/sub 2/(/spl delta/) implies that it is feasible to achieve sublogarithmic time using /spl sigma/(N/sup 3/) processors for matrix multiplication on a realistic system. Algorithms MM/sub 3/, C/sub 1/(/spl epsiv/), and C/sub 2/(/spl delta/) all have o(/spl Nscr//sup 3/) cost and, hence, are very processor efficient. Algorithms MM/sub 1/, MM/sub 3/, and C/sub 1/(/spl epsiv/) are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM/sub 2/ and C/sub 2/(/spl delta/) are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM/sub 2/ and C/sub 2/(/spl delta/) to unbounded integers and reals are also discussed.
Dylan Stow - One of the best experts on this subject based on the ideXlab platform.
-
efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
-
invited efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
Yuan Xie - One of the best experts on this subject based on the ideXlab platform.
-
efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
-
invited efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
Itir Akgun - One of the best experts on this subject based on the ideXlab platform.
-
efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
-
invited efficient system architecture in the era of monolithic 3d dynamic inter tier interconnect and processing in memory
Design Automation Conference, 2019Co-Authors: Dylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Gabriel H LohAbstract:Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and Communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive Parallel Communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.
