The Experts below are selected from a list of 26577 Experts worldwide ranked by ideXlab platform
Mitsumasa Koyanagi - One of the best experts on this subject based on the ideXlab platform.
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Heterogeneous 3D Integration Technology and new 3D LSIs
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:A new 3-D Integration Technology and heterogeneous Integration Technology called a super-chip Integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip Integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip Integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.
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three dimensional hybrid Integration Technology of cmos mems and photonics circuits for optoelectronic heterogeneous integrated systems
IEEE Transactions on Electron Devices, 2011Co-Authors: A. Noriki, Kouji Kiyoyama, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa KoyanagiAbstract:We have developed a new 3-D hybrid Integration Technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid Integration. In order to verify the applied 3-D hybrid Integration Technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale Integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid Integration Technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid Integration Technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.
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Three-dimensional Integration Technology using through-si via based on reconfigured wafer-to-wafer bonding
IEEE Custom Integrated Circuits Conference 2010, 2010Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:Three-dimensional (3-D) Integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D Integration Technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this Technology. In addition, we have developed a new 3-D Integration Technology based on a reconfigured wafer-to-wafer bonding method called a super-chip Integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip Integration.
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New 3D Integration Technology and 3D system LSIs
2009 Symposium on VLSI Technology, 2009Co-Authors: Mitsumasa KoyanagiAbstract:A three-dimensional (3-D) Integration Technology based on the wafer-to-wafer bonding has been developed. Various kinds of 3-D LSI test chips such as 3-D microprocessor chip have been fabricated by using this Technology. In addition, we have developed a new 3-D Integration Technology called super-chip Integration based on the reconfigured wafer- to-wafer bonding in which the reconfigured wafers are produced by simultaneously aligning and bonding more than one thousand of known good dies (KGD's) on a supporting wafer using a self-assembly technique.
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New three-dimensional Integration Technology using reconfigured wafers
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:We have proposed a new three-dimensional (3D) Integration Technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D Integration Technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100 %. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D Integration Technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D Technology).
Tetsu Tanaka - One of the best experts on this subject based on the ideXlab platform.
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Heterogeneous 3D Integration Technology and new 3D LSIs
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:A new 3-D Integration Technology and heterogeneous Integration Technology called a super-chip Integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip Integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip Integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.
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three dimensional hybrid Integration Technology of cmos mems and photonics circuits for optoelectronic heterogeneous integrated systems
IEEE Transactions on Electron Devices, 2011Co-Authors: A. Noriki, Kouji Kiyoyama, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa KoyanagiAbstract:We have developed a new 3-D hybrid Integration Technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid Integration. In order to verify the applied 3-D hybrid Integration Technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale Integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid Integration Technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid Integration Technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.
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Three-dimensional Integration Technology using through-si via based on reconfigured wafer-to-wafer bonding
IEEE Custom Integrated Circuits Conference 2010, 2010Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:Three-dimensional (3-D) Integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D Integration Technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this Technology. In addition, we have developed a new 3-D Integration Technology based on a reconfigured wafer-to-wafer bonding method called a super-chip Integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip Integration.
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Three-dimensional super-chip Integration Technology using self-assembly technique
2008 IEEE Silicon Nanoelectronics Workshop, 2008Co-Authors: Mitsurnasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:We proposed a new three-dimensional (3-D) super-chip Integration Technology using self-assembly technique. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip Integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5 ¿m. We have fabricated 3-D LSI test chips by a super-chip Integration Technology.
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New three-dimensional Integration Technology using reconfigured wafers
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:We have proposed a new three-dimensional (3D) Integration Technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D Integration Technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100 %. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D Integration Technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D Technology).
Takafumi Fukushima - One of the best experts on this subject based on the ideXlab platform.
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Heterogeneous 3D Integration Technology and new 3D LSIs
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:A new 3-D Integration Technology and heterogeneous Integration Technology called a super-chip Integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip Integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip Integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.
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three dimensional hybrid Integration Technology of cmos mems and photonics circuits for optoelectronic heterogeneous integrated systems
IEEE Transactions on Electron Devices, 2011Co-Authors: A. Noriki, Kouji Kiyoyama, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa KoyanagiAbstract:We have developed a new 3-D hybrid Integration Technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid Integration. In order to verify the applied 3-D hybrid Integration Technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale Integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid Integration Technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid Integration Technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.
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Three-dimensional Integration Technology using through-si via based on reconfigured wafer-to-wafer bonding
IEEE Custom Integrated Circuits Conference 2010, 2010Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:Three-dimensional (3-D) Integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D Integration Technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this Technology. In addition, we have developed a new 3-D Integration Technology based on a reconfigured wafer-to-wafer bonding method called a super-chip Integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip Integration.
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Three-dimensional super-chip Integration Technology using self-assembly technique
2008 IEEE Silicon Nanoelectronics Workshop, 2008Co-Authors: Mitsurnasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:We proposed a new three-dimensional (3-D) super-chip Integration Technology using self-assembly technique. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip Integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5 ¿m. We have fabricated 3-D LSI test chips by a super-chip Integration Technology.
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New three-dimensional Integration Technology using reconfigured wafers
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008Co-Authors: Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu TanakaAbstract:We have proposed a new three-dimensional (3D) Integration Technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D Integration Technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100 %. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D Integration Technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D Technology).
Kouji Kiyoyama - One of the best experts on this subject based on the ideXlab platform.
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Characterization of chip-level hetero-Integration Technology for high-speed, highly parallel 3D-stacked image processing system
Technical Digest - International Electron Devices Meeting IEDM, 2012Co-Authors: K.w. Lee, A. Yabata, Tadashi Kamada, Ji Chel Bea, S. Watanabe, Yasuhiko Ohara, Kouji Kiyoyama, Y. Sato, S. Konno, H. HashimotoAbstract:We demonstrate the chip-based 3D heterogeneous Integration Technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
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Chip-based hetero-Integration Technology for high-performance 3D stacked image sensor
2012 2nd IEEE CPMT Symposium Japan, 2012Co-Authors: Yuki Ohara, A. Yabata, Tadashi Kamada, S. Watanabe, Kouji Kiyoyama, Y. Sato, S. Konno, Harufumi Kobayashi, Mariappan Murugesan, H. HashimotoAbstract:We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous Integration Technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
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three dimensional hybrid Integration Technology of cmos mems and photonics circuits for optoelectronic heterogeneous integrated systems
IEEE Transactions on Electron Devices, 2011Co-Authors: A. Noriki, Kouji Kiyoyama, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa KoyanagiAbstract:We have developed a new 3-D hybrid Integration Technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid Integration. In order to verify the applied 3-D hybrid Integration Technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale Integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid Integration Technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid Integration Technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.
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3D Integration Technology for 3D stacked retinal chip
2009 IEEE International Conference on 3D System Integration, 2009Co-Authors: Y. Kaiho, Kouji Kiyoyama, Y. Ohara, H. Takeshita, T. Tanaka, M. KoyanagiAbstract:To recover visual sensation of blind patients, we have proposed a novel three dimensionally (3D) stacked retinal prosthesis chip in which several LSI chips such as consisting of photodetector, signal processing circuit and stimulus current generator are vertically stacked and electrically connected using 3D Integration Technology. In this work, we developed several key process for realizing 3D stacked retinal prosthesis chip. Fine sized Cu TSV of 10 mum width and 30 mum depth was successfully formed from the back side of the thinned prosthesis chip. The prosthesis chip with the back side Cu TSVs was flip-chip bonded to Si substrate/flexible substrate through Cu/Sn micro-bumps for evaluating the feasibility of 3D Integration Technology.
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3D heterogeneous opto-electronic Integration Technology for system-on-silicon (SOS)
2009 IEEE International Electron Devices Meeting (IEDM), 2009Co-Authors: A. Noriki, Kouji Kiyoyama, T. Tanaka, S. Kanno, R. Kobayashi, W-c Jeong, T. Fukushima, M. KoyanagiAbstract:We proposed 3D heterogeneous opto-electronic Integration Technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous Integration Technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.
H. Hashimoto - One of the best experts on this subject based on the ideXlab platform.
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Characterization of chip-level hetero-Integration Technology for high-speed, highly parallel 3D-stacked image processing system
Technical Digest - International Electron Devices Meeting IEDM, 2012Co-Authors: K.w. Lee, A. Yabata, Tadashi Kamada, Ji Chel Bea, S. Watanabe, Yasuhiko Ohara, Kouji Kiyoyama, Y. Sato, S. Konno, H. HashimotoAbstract:We demonstrate the chip-based 3D heterogeneous Integration Technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
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Chip-based hetero-Integration Technology for high-performance 3D stacked image sensor
2012 2nd IEEE CPMT Symposium Japan, 2012Co-Authors: Yuki Ohara, A. Yabata, Tadashi Kamada, S. Watanabe, Kouji Kiyoyama, Y. Sato, S. Konno, Harufumi Kobayashi, Mariappan Murugesan, H. HashimotoAbstract:We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous Integration Technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
