The Experts below are selected from a list of 4263 Experts worldwide ranked by ideXlab platform
W. Geisselhardt - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - New methods for Parallel Pattern fast fault simulation for synchronous sequential circuits
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993Co-Authors: M. Mojtahedi, W. GeisselhardtAbstract:The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a Parallel Pattern simulator with a nonParallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the Parallel part of COMBINED result in a reduction of the number of events. In addition, the nonParallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.
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New methods for Parallel Pattern fast fault simulation for synchronous sequential circuits
Proceedings ETC 93 Third European Test Conference, 1993Co-Authors: M. Mojtahedi, W. GeisselhardtAbstract:The authors present COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED is based on coupling a Parallel Pattern simulator with a non-Parallel simulator. COMBINED runs substantialy faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.
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New methods for Parallel Pattern fast fault simulation for synchronous sequential circuits
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993Co-Authors: M. Mojtahedi, W. GeisselhardtAbstract:The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a Parallel Pattern simulator with a nonParallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the Parallel part of COMBINED result in a reduction of the number of events. In addition, the nonParallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.
R. Kaibel - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - PARIS: a Parallel Pattern fault simulator for synchronous sequential circuits
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, 1991Co-Authors: N. Gouders, R. KaibelAbstract:The authors describe PARIS, a Parallel-Pattern fault simulator for synchronous sequential circuits. PARIS is based on the well-known approach of Parallel Pattern single fault propagation for combinational circuits and features several new techniques. Every single Pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous sequential circuits. >
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PARIS: a Parallel Pattern fault simulator for synchronous sequential circuits
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, 1991Co-Authors: N. Gouders, R. KaibelAbstract:The authors describe PARIS, a Parallel-Pattern fault simulator for synchronous sequential circuits. PARIS is based on the well-known approach of Parallel Pattern single fault propagation for combinational circuits and features several new techniques. Every single Pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous sequential circuits.
Dong Sam Ha - One of the best experts on this subject based on the ideXlab platform.
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VTS - VISION: an efficient Parallel Pattern fault simulator for synchronous sequential circuits
Proceedings 13th IEEE VLSI Test Symposium, 1995Co-Authors: R. Nair, Dong Sam HaAbstract:VISION is an efficient Parallel Pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient Parallel Pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the Parallel Pattern fault simulation for synchronous sequential circuits. According to our experiments, our fault simulator, VISION, which incorporates the four heuristics, is about 1.6 times faster than PARIS for 16 benchmark circuits.
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VISION: an efficient Parallel Pattern fault simulator for synchronous sequential circuits
Proceedings 13th IEEE VLSI Test Symposium, 1995Co-Authors: R. Nair, Dong Sam HaAbstract:VISION is an efficient Parallel Pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient Parallel Pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the Parallel Pattern fault simulation for synchronous sequential circuits. According to our experiments, our fault simulator, VISION, which incorporates the four heuristics, is about 1.6 times faster than PARIS for 16 benchmark circuits.
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an efficient forward fault simulation algorithm based on the Parallel Pattern single fault propagat
International Test Conference, 1991Co-Authors: Dong Sam HaAbstract:In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the Parallel Pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test Patterns simulated at a time, are also presented.
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ITC - AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE Parallel Pattern SINGLE FAULT PROPAGAT
1991 Proceedings. International Test Conference, 1991Co-Authors: Dong Sam HaAbstract:In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the Parallel Pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test Patterns simulated at a time, are also presented.
Cristian Estan - One of the best experts on this subject based on the ideXlab platform.
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Speculative Parallel Pattern Matching
IEEE Transactions on Information Forensics and Security, 2011Co-Authors: Daniel Luchaup, Randy Smith, Cristian EstanAbstract:Intrusion prevention systems (IPSs) determine whether incoming traffic matches a database of signatures, where each signature is a regular expression and represents an attack or a vulnerability. IPSs need to keep up with ever-increasing line speeds, which has lead to the use of custom hardware. A major bottleneck that IPSs face is that they scan incoming packets one byte at a time, which limits their throughput and latency. In this paper, we present a method to search for arbitrary regular expressions by scanning multiple bytes in Parallel using speculation. We break the packet in several chunks, opportunistically scan them in Parallel, and if the speculation is wrong, correct it later. We present algorithms that apply speculation in single-threaded software running on commodity processors as well as algorithms for Parallel hardware. Experimental results show that speculation leads to improvements in latency and throughput in both cases.
M. Mojtahedi - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - New methods for Parallel Pattern fast fault simulation for synchronous sequential circuits
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993Co-Authors: M. Mojtahedi, W. GeisselhardtAbstract:The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a Parallel Pattern simulator with a nonParallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the Parallel part of COMBINED result in a reduction of the number of events. In addition, the nonParallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.
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New methods for Parallel Pattern fast fault simulation for synchronous sequential circuits
Proceedings ETC 93 Third European Test Conference, 1993Co-Authors: M. Mojtahedi, W. GeisselhardtAbstract:The authors present COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED is based on coupling a Parallel Pattern simulator with a non-Parallel simulator. COMBINED runs substantialy faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.
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New methods for Parallel Pattern fast fault simulation for synchronous sequential circuits
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993Co-Authors: M. Mojtahedi, W. GeisselhardtAbstract:The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a Parallel Pattern simulator with a nonParallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the Parallel part of COMBINED result in a reduction of the number of events. In addition, the nonParallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.
