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Claude D'amours - One of the best experts on this subject based on the ideXlab platform.

  • Rapid prototyping of MIMO-OFDM based on Parity Bit selected and permutation spreading
    International Journal of Numerical Modelling: Electronic Networks Devices and Fields, 2015
    Co-Authors: Sherif Moussa, Claude D'amours, Adel Omar Dahmane, Ahmed M. Abdel Razik, Habib Hamam
    Abstract:

    In this paper, a novel MIMO-OFDM transmission scheme is developed to effectively enable multi-access by joint code design across multiple antennas, subcarriers, OFDM frames, and users. It achieves better spectrum efficiency while improving Bit error rate performance. The proposed scheme uses either Parity Bit selected or permutation techniques to assign spreading codes at the transmitter side. As a result, the detection at the receiver is greatly improved because of the fact that identifying the spreading codes directly yields the transmitted data symbols. The paper also investigates the field-programmable gate array implementation of the proposed algorithms; optimization techniques are proposed to reduce area, power, and time. These techniques include a pipelined architecture for inverse FFT/FFT blocks, an efficient low complexity algorithm for despreading based on counters and comparators and an optimized architecture for complex matrix inversion using Gauss-Jordan elimination GJ-elimination. Finally, the fixed-point optimized field-programmable gate array architecture for MIMO-OFDM transceiver is developed, where the maximum allowed performance loss because of quantization is defined, the tradeoffs between BER performance and area reduction are investigated. Copyright © 2015 John Wiley & Sons, Ltd.

  • Turbo receiver for MIMO-CDMA systems employing Parity Bit selected and permutation spreading
    EURASIP Journal on Wireless Communications and Networking, 2013
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper, a turbo receiver for MIMO-CDMA systems employing Parity Bit selected and permutation spreading is proposed. In such systems, spreading codes used by transmit antennas are dependent on the transmitted data. In the proposed system, convolutional coding is used as an outer code, while the Parity Bit selected scheme is used as the inner code. Detection and decoding are performed iteratively for each detected Bit. When Parity Bit selected spreading is used, the Parity Bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. The selected spreading code is then used to spread the signals in all transmit antennas. In contrast, in permutation spreading, a permutation of orthogonal spreading sequences is used in each transmit antenna. In the proposed receiver, soft information passes between the detector and the decoder on multiple iterations. Detection is performed using the received signal from all receive antennas in combination with the extrinsic likelihood provided by a SISO decoder. The turbo receiver is further extended to a multiple user system, where the MAI is estimated in each iteration and subtracted out from the received signal. Simulations show a significant improvement in BER when a turbo receiver is used in these systems.

  • Turbo Receiver for Multicarrier Spread Spectrum Systems Employing Parity Bit Selected Spreading Sequences
    Wireless Personal Communications, 2012
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper a turbo receiver for multicarrier spread spectrum systems employing Parity Bit selected spreading code (MC-SS-PB) is proposed where detection and decoding are performed iteratively for each detected Bit in the receiver. In MC-SS-PB systems, the Parity Bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. The selected spreading code is then used to spread the signals in all subcarriers. In the proposed receiver, soft information passes between the detector and the decoder on multiple iterations. Detection is performed by using the received signal in combination with the extrinsic likelihood provided by a soft input soft output decoder. The turbo receiver is further extended to a multiple user system where the multiple access interference is estimated in each iteration and subtracted out from the received signal. Simulations show a significant reduction in Bit error rates when a turbo receiver is used in these systems.

  • MIMO-OFDM scheme based on Parity Bit selected spreading
    2012 2nd International Conference on Consumer Electronics Communications and Networks (CECNet), 2012
    Co-Authors: Sherif Moussa, Claude D'amours, Adel Omar Dahmane, Habib Hamam
    Abstract:

    In this paper, a novel transmission scheme is developed to effectively combine Parity Bit selected spreading technique and MIMO-OFDM to obtain improved Bit error rate performance in the presence of frequency selective fading channels with low system complexity. Unlike conventional MIMO-OFDMA, where users are separated in different frequency bands (subchannels), and each user is coded separately using STBC or SFBC, the proposed new scheme enables multi access by joint code design across multiple antennas, subcarriers, and users. Such system will benefit from the combined space and frequency domain freedom as well as multiuser diversity. Hence, better spectrum efficiency is achieved while improving Bit error rate performance with respect to signal-to-interference ratio.

  • Turbo Receiver for DS-SS Systems Employing Parity Bit Selected Spreading Codes
    IEEE Communications Letters, 2012
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper a turbo receiver for direct sequence spread spectrum (DS-SS) systems employing Parity Bit selected spreading code (SS-PB) is proposed where detection and decoding are performed iteratively for each detected Bit in the receiver. In SS-PB systems, Parity Bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. Performance evaluation in both additive white Gaussian noise (AWGN) and fading channels show a significant reduction in Bit error rates (BER) when a turbo receiver is used in these systems.

Alireza Mirzaee - One of the best experts on this subject based on the ideXlab platform.

  • Turbo receiver for MIMO-CDMA systems employing Parity Bit selected and permutation spreading
    EURASIP Journal on Wireless Communications and Networking, 2013
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper, a turbo receiver for MIMO-CDMA systems employing Parity Bit selected and permutation spreading is proposed. In such systems, spreading codes used by transmit antennas are dependent on the transmitted data. In the proposed system, convolutional coding is used as an outer code, while the Parity Bit selected scheme is used as the inner code. Detection and decoding are performed iteratively for each detected Bit. When Parity Bit selected spreading is used, the Parity Bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. The selected spreading code is then used to spread the signals in all transmit antennas. In contrast, in permutation spreading, a permutation of orthogonal spreading sequences is used in each transmit antenna. In the proposed receiver, soft information passes between the detector and the decoder on multiple iterations. Detection is performed using the received signal from all receive antennas in combination with the extrinsic likelihood provided by a SISO decoder. The turbo receiver is further extended to a multiple user system, where the MAI is estimated in each iteration and subtracted out from the received signal. Simulations show a significant improvement in BER when a turbo receiver is used in these systems.

  • Turbo Receiver for Multicarrier Spread Spectrum Systems Employing Parity Bit Selected Spreading Sequences
    Wireless Personal Communications, 2012
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper a turbo receiver for multicarrier spread spectrum systems employing Parity Bit selected spreading code (MC-SS-PB) is proposed where detection and decoding are performed iteratively for each detected Bit in the receiver. In MC-SS-PB systems, the Parity Bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. The selected spreading code is then used to spread the signals in all subcarriers. In the proposed receiver, soft information passes between the detector and the decoder on multiple iterations. Detection is performed by using the received signal in combination with the extrinsic likelihood provided by a soft input soft output decoder. The turbo receiver is further extended to a multiple user system where the multiple access interference is estimated in each iteration and subtracted out from the received signal. Simulations show a significant reduction in Bit error rates when a turbo receiver is used in these systems.

  • Turbo Receiver for DS-SS Systems Employing Parity Bit Selected Spreading Codes
    IEEE Communications Letters, 2012
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper a turbo receiver for direct sequence spread spectrum (DS-SS) systems employing Parity Bit selected spreading code (SS-PB) is proposed where detection and decoding are performed iteratively for each detected Bit in the receiver. In SS-PB systems, Parity Bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. Performance evaluation in both additive white Gaussian noise (AWGN) and fading channels show a significant reduction in Bit error rates (BER) when a turbo receiver is used in these systems.

  • VTC Fall - A Multiuser Receiver for CDMA Systems with Parity Bit Selected Spreading Sequences
    2010 IEEE 72nd Vehicular Technology Conference - Fall, 2010
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    In this paper we propose a multiuser receiver using multistage detection and interference cancellation for direct-sequence code-division multiple-access (DS/CDMA) systems with Parity Bit selected spreading sequences in synchronous channels. In a CDMA system with Parity Bit selected spreading sequences (CDMA/PB), the spreading code used by each user depends on the transmitted data Bits and it is selected from a set of mutually orthogonal spreading waveforms allocated to each user. Multistage parallel interference cancellation (PIC) detector is used to estimate and subtract out all multiple-access interference (MAI) for each user in parallel. The performance of the proposed system is compared with the conventional uncoded CDMA systems.

  • Soft output detector for Parity Bit selected CDMA system
    2009 11th Canadian Workshop on Information Theory, 2009
    Co-Authors: Alireza Mirzaee, Claude D'amours
    Abstract:

    This paper investigates the performance of the Parity Bit selected Code Division Multiple Access (PB-CDMA) system when a soft output detector based on Log Likelihood Ratio (LLR) calculation is employed. In this system, information Bits are convolutionally encoded prior to being used in the Parity Bit selected Direct Sequence Spread Spectrum (DS-SS) system. Reliability of the detected Bits in the receiver is calculated in the form of LLRs and then used as the input of a soft input Viterbi decoder. The performance of the proposed system is compared to conventional coded spread spectrum systems where no Parity Bit selected spreading sequence is used. Numerical results show that the proposed system can be used to improve the capacity of a Code Division Multiple Access (CDMA) system in terms of the number of simultaneously transmitting users.

Claude Damours - One of the best experts on this subject based on the ideXlab platform.

Jeanyves Chouinard - One of the best experts on this subject based on the ideXlab platform.

Pedro Reviriego - One of the best experts on this subject based on the ideXlab platform.

  • Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP)
    IEEE Transactions on Emerging Topics in Computing, 2019
    Co-Authors: Shanshan Liu, Pedro Reviriego, Fabrizio Lombardi
    Abstract:

    Emerging memory technologies rely on Multilevel Cells (MLC) to achieve high density; the use of multiple levels per cell allows storage of multiple Bits, but it also reduces the margins and makes it error prone. Error control codes (including error correction and detection codes) can be used to protect MLC memories from errors; however, most existing coding schemes have been designed for traditional binary memories (so storing a single Bit). In MLC memories, errors cause a change from a level to an adjacent level or to the next one (depending on the employed technology), so they are often referred to as limited magnitude errors. For a binary coding of levels to Bits, these limited magnitude errors can corrupt several Bits making traditional coding schemes inefficient. In this paper, error detection of MLC memories is considered when a binary encoding of levels to Bits is used and two new schemes are proposed: One-Bit Parity (OBP) and Two-Bit Parity (TBP). The first scheme targets errors of magnitude-1 for detection using a single Parity Bit that checks only one Bit per cell. The second scheme detects both magnitude-1 and -2 errors using only two Parity Bits. Both schemes are compared to existing alternatives, namely Gray coding combined with a single Parity Bit (GP) for OBP and Interleaved Parity (IP) for TBP. The results show that OBP reduces the encoding and error detection circuitry complexity and delay, while TBP additionally reduces the number of Parity Bits for some configurations. Therefore, OBP and TBP can be efficient alternatives for detection of limited magnitude errors in MLC memories that use a binary encoding of levels to Bits.

  • Efficient error detection in multiple way tables
    Electronics Letters, 2015
    Co-Authors: Pedro Reviriego, Juan Antonio Maestro
    Abstract:

    Multiple way tables in which items can be placed on several buckets are used in many computing applications. Some examples are cache memories and multiple hash tables structures. In most cases, the items are stored in electronic memories that are prone to soft errors that can corrupt the stored items. To avoid data corruption, memories can be protected with a Parity Bit or with an error correction code. It is shown that most single Bit errors can be detected in multiple way tables without adding a Parity Bit. This can be done by placing the items in a predetermined order in the multiple ways of the table.

  • FastTag: A Technique to Protect Cache Tags Against Soft Errors
    IEEE Transactions on Device and Materials Reliability, 2014
    Co-Authors: Pedro Reviriego, Salvatore Pontarelli, Marco Ottavi, Juan Antonio Maestro
    Abstract:

    Cache memories are very relevant components in modern processors, and therefore, their protection against soft errors is important to ensure reliability. One important element in caches is the tag fields, which are critical to keep data integrity and achieve a high hit ratio. To protect them against soft errors, a Parity Bit or a single error correction (SEC) code is commonly used. In that case, on each cache access, the Parity Bit is checked or the SEC code decoded on each cache way to detect and correct errors. In this paper, FastTag, a novel approach to protect cache tags is presented and evaluated. The proposed scheme computes the Parity or SEC Bits on the incoming address and compares the result with the tag and Parity Bits stored in each cache way. This avoids Parity recomputation or SEC decoding, thus reducing the circuit complexity. This is corroborated by the evaluation results that show how FastTag requires an area, delay, and power overhead much lower than the conventional techniques that are currently used.

  • Reducing the Cost of Single Error Correction With Parity Sharing
    IEEE Transactions on Device and Materials Reliability, 2013
    Co-Authors: Pedro Reviriego, Juan Antonio Maestro, Salvatore Pontarelli, Marco Ottavi
    Abstract:

    Error correction codes (ECCs) are commonly used to protect memory devices from errors. The most commonly used codes are a simple Parity Bit and single-error-correction (SEC) codes. A Parity Bit enables single-Bit error detection, whereas a SEC code can correct one-Bit errors. A SEC code requires more additional Bits per word and also more complex decoding that impacts delay. A tradeoff between both schemes is the use of a product code based on a combination of two Parity Bits. This approach reduces the memory overhead at the expense of a more complex access procedure. In this letter, an alternative scheme based on the use of Parity sharing is proposed and evaluated. The results show that the new approach significantly reduces the memory overhead and is also capable of correcting single-Bit errors.

  • Reliability analysis of memories protected with BICS and a per-word Parity Bit
    ACM Transactions on Design Automation of Electronic Systems, 2010
    Co-Authors: Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley
    Abstract:

    This article presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word Parity Bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for which two analytic models are proposed. A simple model, similar to the one traditionally used for memories protected with scrubbing, is proposed for the low error rate case. A more complex Markov model is proposed for the high error rate case. The accuracy of the models is checked using a wide set of simulations. The results presented in this article allow fast estimation of MTTF enabling design of optimal memory configurations to meet specified MTTF goals at minimum cost. Additionally the power consumption of memories protected with BICS is compared to that of memories using scrubbing in terms of the number of read cycles needed in both configurations.