The Experts below are selected from a list of 11520 Experts worldwide ranked by ideXlab platform

C Richard J Shi - One of the best experts on this subject based on the ideXlab platform.

  • a high throughput low power fully parallel 1024 bit 1 2 rate low density Parity Check Code deCoder in 3 dimensional integrated circuits
    Asia and South Pacific Design Automation Conference, 2006
    Co-Authors: Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, C Richard J Shi
    Abstract:

    A 1024-bit, 1/2 -rate fully parallel low density Parity Check (LDPC) Code deCoder has been designed and implemented using a 3D 0.18/spl mu/m fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D deCoder with about 8M transistors was simulated to have a high throughput of 2Gb/s and a low power consumption of only 430mW using 6.4/spl mu/m by 6.3/spl mu/m of die area. The 3D implementation is estimated to offer more than 10/spl times/ power-delay-area product improvement over its corresponding 2D implementation. This first large-scale 3D ASIC with fine-grain (5/spl mu/m) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2D design flow combined with the needed 3D-design point tools.

  • an fpga implementation of low density Parity Check Code deCoder with multi rate capability
    Asia and South Pacific Design Automation Conference, 2005
    Co-Authors: Lei Yang, Manyuan Shen, Hui Liu, C Richard J Shi
    Abstract:

    With superior error correction capability, low-density Parity-Check (LDPC) has initiated wide scale interests in wireless telecommunication fields. In the past, various structures of single Code rate LDPC deCoders have been implemented for different applications. However, in order to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC deCoders that can operate in both high and low Code rates are desired. In this paper, a new multi-rate LDPC deCoder architecture is presented and implemented in a Xilinx FPGA device. Through selection pins, three operating modes with the irregular 1/2 rate, regular 5/8 rate and regular 7/8 rate are supported. The measurement results show LDPC deCoder can achieve BER below 10-5 at SNR of 1.4dB in the most critical case with the irregular 1/2 mode.

Hyuck M Kwon - One of the best experts on this subject based on the ideXlab platform.

  • an improved quasi cyclic low density Parity Check Code for memory channels
    Vehicular Technology Conference, 2004
    Co-Authors: M Jayabalan, Hyuck M Kwon
    Abstract:

    This paper presents an improved construction of circulant sub-matrices based quasi-cyclic low density Parity Check Codes (QC-LDPC) under fading channels. The proposed construction yields a performance gain of about 2 to 5 dB at a 10/sup -4/ bit error rate (BER). This paper also proposes a decoding method to reduce the implementation complexity in the belief propagation algorithm. Furthermore, this paper studies the performance of circulant sub-matrices based QC-LDPC Codes at higher rates under AWGN and fading channels.

C J R Shi - One of the best experts on this subject based on the ideXlab platform.

  • implementing a 2 gbs 1024 bit rate low density Parity Check Code deCoder in three dimensional integrated circuits
    International Conference on Computer Design, 2007
    Co-Authors: Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, R Panda, C J R Shi
    Abstract:

    A 1024-bit, 1/2-rate fully parallel low-density Parity-Check (LDPC) Code deCoder has been designed and implemented using a three-dimensional (3D) 0.18 mum fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The 3D-IC deCoder was implemented with about 8M transistors, placed on three tiers, each with one active layer and three metal layers, using 6.9 mm by 7.0 mm of die area. It was simulated to have a 2 Gbps throughput, and consume only 260 mW. This first large-scale 3D application-specific integrated circuit (ASIC) with fine-grain (5mum) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2-D design flow combined with the needed 3D-design tools. The 3D implementation is estimated to offer more than 10 xpower-delay-area product improvement over its corresponding 2D implementation. The work demonstrated the benefits of fine-grain 3D integration for interconnect-heavy very-large-scale digital ASIC implementation.

  • Code construction and fpga implementation of a low error floor multi rate low density Parity Check Code deCoder
    IEEE Transactions on Circuits and Systems I-regular Papers, 2006
    Co-Authors: Lei Yang, Hui Liu, C J R Shi
    Abstract:

    With the superior error correction capability, low-density Parity-Check (LDPC) Codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single Code-rate LDPC deCoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC deCoders that can operate at both high and low Code rates are desirable. In this paper, a 9-k Code length multi-rate LDPC deCoder architecture is presented and implemented on a Xilinx field-programmable gate array device. Using pin selection, three operating modes, namely, the irregular 1/2 Code mode, the regular 5/8 Code mode, and the regular 7/8 Code mode, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC Code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented deCoder is tested in an experimental LDPC orthogonal frequency division multiplexing system and achieves the superior measured performance of block error rate below 10/sup -7/ at signal-to-noise ratio of 1.8 dB.

Jin Sha - One of the best experts on this subject based on the ideXlab platform.

  • vlsi design for low density Parity Check Code decoding
    IEEE Circuits and Systems Magazine, 2011
    Co-Authors: Zhongfeng Wang, Zhiqiang Cui, Jin Sha
    Abstract:

    Low-Density Parity-Check (LDPC) Code, being one of the most promising near-Shannon limit error correction Codes (ECCs) in practice, has attracted tremendous attention in both academia and industry since its rediscovery in middle 1990's. Owning excellent coding gain, LDPC Code also has very low error floor, and inherent parallizable decoding schemes. Compared to other ECCs such as Turbo Codes, BCH Codes and RS Codes, LDPC Code has many more varieties in Code construction, which result in various optimum decoding architectures associated with different structures of the Parity-Check matrix. In this work, we first provide an overview of typical LDPC Code structures and commonly-used LDPC decoding algorithms. We then discuss efficient VLSI architectures for random-like Codes and structured LDPC Codes. We further present layered decoding schemes and corresponding VLSI architectures. Finally we briefly address non-binary LDPC decoding and multi-rate LDPC deCoder design.

Lei Yang - One of the best experts on this subject based on the ideXlab platform.

  • Code construction and fpga implementation of a low error floor multi rate low density Parity Check Code deCoder
    IEEE Transactions on Circuits and Systems I-regular Papers, 2006
    Co-Authors: Lei Yang, Hui Liu, C J R Shi
    Abstract:

    With the superior error correction capability, low-density Parity-Check (LDPC) Codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single Code-rate LDPC deCoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC deCoders that can operate at both high and low Code rates are desirable. In this paper, a 9-k Code length multi-rate LDPC deCoder architecture is presented and implemented on a Xilinx field-programmable gate array device. Using pin selection, three operating modes, namely, the irregular 1/2 Code mode, the regular 5/8 Code mode, and the regular 7/8 Code mode, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC Code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented deCoder is tested in an experimental LDPC orthogonal frequency division multiplexing system and achieves the superior measured performance of block error rate below 10/sup -7/ at signal-to-noise ratio of 1.8 dB.

  • an fpga implementation of low density Parity Check Code deCoder with multi rate capability
    Asia and South Pacific Design Automation Conference, 2005
    Co-Authors: Lei Yang, Manyuan Shen, Hui Liu, C Richard J Shi
    Abstract:

    With superior error correction capability, low-density Parity-Check (LDPC) has initiated wide scale interests in wireless telecommunication fields. In the past, various structures of single Code rate LDPC deCoders have been implemented for different applications. However, in order to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC deCoders that can operate in both high and low Code rates are desired. In this paper, a new multi-rate LDPC deCoder architecture is presented and implemented in a Xilinx FPGA device. Through selection pins, three operating modes with the irregular 1/2 rate, regular 5/8 rate and regular 7/8 rate are supported. The measurement results show LDPC deCoder can achieve BER below 10-5 at SNR of 1.4dB in the most critical case with the irregular 1/2 mode.