The Experts below are selected from a list of 201 Experts worldwide ranked by ideXlab platform

Yingke Gao - One of the best experts on this subject based on the ideXlab platform.

  • Path Constraint solving based test generation for observability enhanced branch coverage
    VLSI Test Symposium, 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

  • VTS - Path Constraint solving based test generation for observability-enhanced branch coverage
    2016 IEEE 34th VLSI Test Symposium (VTS), 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

Yanhong Zhou - One of the best experts on this subject based on the ideXlab platform.

  • functional test generation for hard to reach states using Path Constraint solving
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang
    Abstract:

    Test generation for hard-to-reach states is important in functional verification. In this paper, we present a Path Constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for Path Constraint extraction and mutation, and uses a sequential Path Constraint extractor to generate a set of valid input vectors for exploring different simulation Paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods.

  • Path Constraint solving based test generation for observability enhanced branch coverage
    VLSI Test Symposium, 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

  • VTS - Path Constraint solving based test generation for observability-enhanced branch coverage
    2016 IEEE 34th VLSI Test Symposium (VTS), 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

  • Path Constraint solving based test generation for hard to reach states
    Asian Test Symposium, 2013
    Co-Authors: Yanhong Zhou, Tiancheng Wang
    Abstract:

    Test generation for hard-to-reach states has been one of the hardest tasks in functional verification. In this paper, we present PACOST, a Path Constraint Solving based Test generation method which operates in an abstraction-guided simulation framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation in a Path Constraint solver to generate a set of valid input vectors for exploring different simulation Paths, followed by next state selection considering abstract distances. In addition, two backtracking strategies are proposed to alleviate the dead end problem and ensure fast converge to the target state. Experimental results show that PACOST is effective in covering hard-to-reach states.

  • Asian Test Symposium - Path Constraint Solving Based Test Generation for Hard-to-Reach States
    2013 22nd Asian Test Symposium, 2013
    Co-Authors: Yanhong Zhou, Tiancheng Wang
    Abstract:

    Test generation for hard-to-reach states has been one of the hardest tasks in functional verification. In this paper, we present PACOST, a Path Constraint Solving based Test generation method which operates in an abstraction-guided simulation framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation in a Path Constraint solver to generate a set of valid input vectors for exploring different simulation Paths, followed by next state selection considering abstract distances. In addition, two backtracking strategies are proposed to alleviate the dead end problem and ensure fast converge to the target state. Experimental results show that PACOST is effective in covering hard-to-reach states.

Bo Liu - One of the best experts on this subject based on the ideXlab platform.

  • Path Constraint solving based test generation for observability enhanced branch coverage
    VLSI Test Symposium, 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

  • VTS - Path Constraint solving based test generation for observability-enhanced branch coverage
    2016 IEEE 34th VLSI Test Symposium (VTS), 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

Tiancheng Wang - One of the best experts on this subject based on the ideXlab platform.

  • functional test generation for hard to reach states using Path Constraint solving
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang
    Abstract:

    Test generation for hard-to-reach states is important in functional verification. In this paper, we present a Path Constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for Path Constraint extraction and mutation, and uses a sequential Path Constraint extractor to generate a set of valid input vectors for exploring different simulation Paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods.

  • Path Constraint solving based test generation for observability enhanced branch coverage
    VLSI Test Symposium, 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

  • VTS - Path Constraint solving based test generation for observability-enhanced branch coverage
    2016 IEEE 34th VLSI Test Symposium (VTS), 2016
    Co-Authors: Yanhong Zhou, Tiancheng Wang, Bo Liu, Yingke Gao
    Abstract:

    Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a Path Constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle Path Constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

  • Path Constraint solving based test generation for hard to reach states
    Asian Test Symposium, 2013
    Co-Authors: Yanhong Zhou, Tiancheng Wang
    Abstract:

    Test generation for hard-to-reach states has been one of the hardest tasks in functional verification. In this paper, we present PACOST, a Path Constraint Solving based Test generation method which operates in an abstraction-guided simulation framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation in a Path Constraint solver to generate a set of valid input vectors for exploring different simulation Paths, followed by next state selection considering abstract distances. In addition, two backtracking strategies are proposed to alleviate the dead end problem and ensure fast converge to the target state. Experimental results show that PACOST is effective in covering hard-to-reach states.

  • Asian Test Symposium - Path Constraint Solving Based Test Generation for Hard-to-Reach States
    2013 22nd Asian Test Symposium, 2013
    Co-Authors: Yanhong Zhou, Tiancheng Wang
    Abstract:

    Test generation for hard-to-reach states has been one of the hardest tasks in functional verification. In this paper, we present PACOST, a Path Constraint Solving based Test generation method which operates in an abstraction-guided simulation framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation in a Path Constraint solver to generate a set of valid input vectors for exploring different simulation Paths, followed by next state selection considering abstract distances. In addition, two backtracking strategies are proposed to alleviate the dead end problem and ensure fast converge to the target state. Experimental results show that PACOST is effective in covering hard-to-reach states.

Dae Hee Youn - One of the best experts on this subject based on the ideXlab platform.

  • HMM with Global Path Constraint in Viterbi Decoding for Insolated Word Recognition
    The Journal of the Acoustical Society of Korea, 1994
    Co-Authors: Weon-goo Kim, Dong-soon Ahn, Dae Hee Youn
    Abstract:

    Hidden Markov Models (HMM's) with explicit state duration density (HMM/SD) can represent the time-varying characteristics of speech signals more accurately. However, such an advantage is reduced in relatively smooth state duration densities or ling bounded duration. To solve this problem, we propose HMM's with global Path Constraint (HMM/GPC) where the transition between states occur only within prescribed time slots. HMM/GPC explicitly limits state durations and accurately describes the temproal structure of speech simply and efficiently. HMM's formed by combining HMM/GPC with HMM/SD are also presented (HMM/SD+GPC) and performances are compared. HMM/GPC can be implemented with slight modifications to the conventional Viterbi algorithm. HMM/GPC and HMM/SD_GPC not only show superior performance than the conventional HMM and HMM/SD but also require much less computation. In the speaket independent isolated word recognition experiments, the minimum recognition eror rate of HMM/GPC(1.6%) is 1.1% lower than the conventional HMM's and the required computation decreased about 57%.

  • ICASSP (1) - HMM with global Path Constraint in Viterbi decoding for isolated word recognition
    Proceedings of ICASSP '94. IEEE International Conference on Acoustics Speech and Signal Processing, 1
    Co-Authors: Weon-goo Kim, Jeung-yoon Choi, Dae Hee Youn
    Abstract:

    Hidden Markov models (HMMs) with explicit state duration density (HMM/SD) can represent the time-varying characteristics of speech signals more accurately. However, such an advantage is reduced in relatively smooth state duration densities or long bounded duration. To solve this problem, the authors propose HMMs with global Path Constraint (HMM/GPC) where the transition between states occur only within prescribed time slots. HMM/GPC explicitly limits state durations and accurately describes the temporal structure of speech simply and efficiently. HMMs formed by combining HMM/GPC with HMM/SD are also presented (HMM/SD+GPC) and performances are compared. HMM/GPC can be implemented with slight modifications to the conventional Viterbi algorithm. HMM/GPC and HMM/SD+GPC not only show superior performance than the conventional HMM and HMM/SD but also require much less computation. >