The Experts below are selected from a list of 29778 Experts worldwide ranked by ideXlab platform
Oliver Diessel - One of the best experts on this subject based on the ideXlab platform.
-
modeling dynamically reconfigurable systems for simulation based Functional Verification
Field-Programmable Custom Computing Machines, 2011Co-Authors: Lingkan Gong, Oliver DiesselAbstract:Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the Functional Verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made Functional Verification dependent on the physical implementation. This paper studies simulation as the most fundamental approach to the Functional Verification of DRS. The main contribution of this paper is in proposing a Verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.
-
FCCM - Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011Co-Authors: Lingkan Gong, Oliver DiesselAbstract:Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the Functional Verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made Functional Verification dependent on the physical implementation. This paper studies simulation as the most fundamental approach to the Functional Verification of DRS. The main contribution of this paper is in proposing a Verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.
Elmar U. K. Melcher - One of the best experts on this subject based on the ideXlab platform.
-
SBCCI - A Distributed Functional Verification Environment for the Design of System-on-Chip in Heterogeneous Architectures
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 2018Co-Authors: Thiago Werlley B. Silva, Elmar U. K. Melcher, Daniel C. Morais, Halamo G. R. Andrade, Felipe C A Nunes, Antonio Marcus Nogueira Lima, Alisson V. BritoAbstract:In complex System-on-a-Chip (SoC) projects, the conclusion of the project depends on the Functional Verification phase, which takes a long time. Synchronizing distributed and heterogeneous components in a Functional Verification environment might not be a simple task. This work aims to present a distributed Verification environment that allows the integration of heterogeneous components. In this environment, it is possible to perform the Functional Verification of multiple components in heterogeneous architectures in parallel and distributed fashion. For this, an intercommunication framework already developed by the authors was used, based on the High Level Architecture (IEEE 1516) standard. Thus, this article also demonstrates how the proposed architecture abstracts communication and synchronization details to make the Functional Verification process in distributed components as straightforward as possible. As a demonstration of the developed solution, an experiment is presented with the Functional Verification of parallel algorithms in GPU and in FPGA, besides the Verification using a CPU.
-
SBCCI - Functional Verification of power gate design in SystemC RTL
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design Chip on the Dunes - SBCCI '09, 2009Co-Authors: George Sobral Silveira, Alisson V. Brito, Elmar U. K. MelcherAbstract:With the growth of number of transistors, thermal density and market drive towards battery power, the necessity to develop low power integrated circuits is evident. There are several methodologies and techniques that help in the development of this type of SoC. There is consensus that the techniques when applied in the initial phases of the design flow, especially in design and architecture of the system have a higher impact factor in relation to those applied during the implementation or layout phase. Considering this fact, the possibility to accomplish Functional Verification of the system with low power design modeled in TLM and RTL is attractive. The purpose of this paper is to show a method for Functional Verification of power gate design in RTL. A case study is presented to demonstrate the application of power gate using new features for the OSCI SystemC simulator developed for this purpose and the accomplishment of the Functional Verification of the design using the VeriSC methodology.
-
SMC - Functional Verification methodology using Hierarchical Coloured Petri Nets-based testbenches
2008 IEEE International Conference on Systems Man and Cybernetics, 2008Co-Authors: C.l. Rodrigues, Fábio Morais, L.m.l. Silva, K.r.g. Da Silva, J.c.a. De Figueiredo, Dalton Guerrero, Elmar U. K. MelcherAbstract:We present a Functional Verification methodology that employs hierarchical coloured petri nets (HCPN) to describe the testbench. By this way, we are avoiding the absence of formal techniques concerning the testbench description and keeping a high-level of abstraction that is required in this phase of the project. The hierarchical (de)composition is the solution to deal with large designs. The methodology prescribes a way to (de)compose the testbench that promotes incremental development and reuse of testbench elements. Furthermore, our methodology provides tool support for the testbench creation. Experimental results concerning the Functional Verification of the MPEG 4 video decoder are presented.
-
an automatic testbench generation tool for a systemc Functional Verification methodology
Symposium on Integrated Circuits and Systems Design, 2004Co-Authors: Karina R G Da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves PimentaAbstract:The advent of new 90nm/130nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, Functional Verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable Verification. In this paper we propose an automatic Verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint Functional Verification. Our approach uses the SystemC Verification Library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.
-
SBCCI - An automatic testbench generation tool for a SystemC Functional Verification methodology
Proceedings of the 17th symposium on Integrated circuits and system design - SBCCI '04, 2004Co-Authors: Karina R G Da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves PimentaAbstract:The advent of new 90 nm/130 nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, Functional Verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable Verification. In this paper we propose an automatic Verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint Functional Verification. Our approach uses the systemC Verification library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.
Lingkan Gong - One of the best experts on this subject based on the ideXlab platform.
-
modeling dynamically reconfigurable systems for simulation based Functional Verification
Field-Programmable Custom Computing Machines, 2011Co-Authors: Lingkan Gong, Oliver DiesselAbstract:Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the Functional Verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made Functional Verification dependent on the physical implementation. This paper studies simulation as the most fundamental approach to the Functional Verification of DRS. The main contribution of this paper is in proposing a Verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.
-
FCCM - Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011Co-Authors: Lingkan Gong, Oliver DiesselAbstract:Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the Functional Verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made Functional Verification dependent on the physical implementation. This paper studies simulation as the most fundamental approach to the Functional Verification of DRS. The main contribution of this paper is in proposing a Verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.
Harry Foster - One of the best experts on this subject based on the ideXlab platform.
-
2018 fpga Functional Verification trends
Microprocessor Test and Verification, 2018Co-Authors: Harry FosterAbstract:While multiple studies on IC/ASIC Functional Verification trends have been published, to our knowledge, there are no published studies specifically focused on FPGA Verification trends. To address this dearth of information, this paper presents the results from a recent large industry study. The findings from this study provide invaluable insight into the state of today's FPGA market in terms of both design and Verification trends.
-
MTV - 2018 FPGA Functional Verification Trends
2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV), 2018Co-Authors: Harry FosterAbstract:While multiple studies on IC/ASIC Functional Verification trends have been published, to our knowledge, there are no published studies specifically focused on FPGA Verification trends. To address this dearth of information, this paper presents the results from a recent large industry study. The findings from this study provide invaluable insight into the state of today's FPGA market in terms of both design and Verification trends.
-
trends in Functional Verification a 2014 industry study
Design Automation Conference, 2015Co-Authors: Harry FosterAbstract:Technical publications often make either subjective or unsubstantiated claims about today's Functional Verification process---such as, 70 percent of a project's overall effort is spent in Verification. Yet, there are very few credible industry studies that quantitatively provide insight into the Functional Verification process in terms of Verification technology adoption, effort, and effectiveness. To address this dearth of knowledge, a recent world-wide, double-blind, Functional Verification study was conducted, covering all electronic industry market segments. To our knowledge, this is the largest independent Functional Verification study ever conducted. This paper presents the findings from our 2014 study and provides invaluable insight into the state of the electronic industry today in terms of both design and Verification trends.
-
DAC - Trends in Functional Verification: a 2014 industry study
Proceedings of the 52nd Annual Design Automation Conference, 2015Co-Authors: Harry FosterAbstract:Technical publications often make either subjective or unsubstantiated claims about today's Functional Verification process---such as, 70 percent of a project's overall effort is spent in Verification. Yet, there are very few credible industry studies that quantitatively provide insight into the Functional Verification process in terms of Verification technology adoption, effort, and effectiveness. To address this dearth of knowledge, a recent world-wide, double-blind, Functional Verification study was conducted, covering all electronic industry market segments. To our knowledge, this is the largest independent Functional Verification study ever conducted. This paper presents the findings from our 2014 study and provides invaluable insight into the state of the electronic industry today in terms of both design and Verification trends.
Geoff Barrett - One of the best experts on this subject based on the ideXlab platform.
-
Functional Verification methodology of chameleon processor
Design Automation Conference, 1996Co-Authors: Francoise Casaubieilh, Anthony Mcisaac, Mike Benjamin, Mike G Bartley, Francois Pogodalla, Frederic Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gerard Mas, Geoff BarrettAbstract:Functional Verification of the new generation microprocessor developed by SGS-Thomson Microelectronics makes extensive use of advanced technologies. This paper presents a global overview of the methodology and focuses on three main aspects: Use of acceleration and emulation technologies for the Verification of the VRDL specification in the early stages of the design; development and use of sequential Verification methods built upon a commercially available formal proof tool; and extensive use of combinational proof for circuit-level Verification, in conjunction with transistor abstraction.
-
DAC - Functional Verification methodology of Chameleon processor
Proceedings of the 33rd annual conference on Design automation conference - DAC '96, 1996Co-Authors: Francoise Casaubieilh, Anthony Mcisaac, Mike Benjamin, Mike G Bartley, Francois Pogodalla, Frederic Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gerard Mas, Geoff BarrettAbstract:Functional Verification of the new generation microprocessor developed by SGS-Thomson Microelectronics makes extensive use of advanced technologies. This paper presents a global overview of the methodology and focuses on three main aspects: Use of acceleration and emulation technologies for the Verification of the VRDL specification in the early stages of the design; development and use of sequential Verification methods built upon a commercially available formal proof tool; and extensive use of combinational proof for circuit-level Verification, in conjunction with transistor abstraction.
