The Experts below are selected from a list of 162 Experts worldwide ranked by ideXlab platform
J N Chung - One of the best experts on this subject based on the ideXlab platform.
-
Investigation of laminar flow in microtubes with random rough surfaces
Microfluidics and Nanofluidics, 2009Co-Authors: Renqiang Xiong, J N ChungAbstract:A new approach of numerically generating a microtube with three-dimensional random surface Roughness is presented. In this approach, we combined a bi-cubic Coons patch with Gaussian distributed Roughness heights. Two random Roughness generation methods are studied. A computational fluid dynamic solver is used to solve the 3-D N–S equations for the flow through the generated rough microtubes with D = 50 μm and L = 100 μm. The effects of the Peak Roughness height, H , asperities spacing in the θ direction, S _ θ , and Z direction, S _ Z , standard deviation of the Gaussian distribution, σ , arithmetical mean Roughness, R _ a , on the Poiseuille number, Po are investigated. It is found that when H/D
-
Investigation of laminar flow in microtubes with random rough surfaces
Microfluidics and Nanofluidics, 2009Co-Authors: Renqiang Xiong, J N ChungAbstract:A new approach of numerically generating a microtube with three-dimensional random surface Roughness is presented. In this approach, we combined a bi-cubic Coons patch with Gaussian distributed Roughness heights. Two random Roughness generation methods are studied. A computational fluid dynamic solver is used to solve the 3-D N–S equations for the flow through the generated rough microtubes with D = 50 μm and L = 100 μm. The effects of the Peak Roughness height, H, asperities spacing in the θ direction, S θ , and Z direction, S Z , standard deviation of the Gaussian distribution, σ, arithmetical mean Roughness, R a, on the Poiseuille number, Po are investigated. It is found that when H/D < 5% the Po number can still be predicted by the conventional flow theory if the mean diameter of rough microtubes, D m, is used to be the hydraulic diameter D h. When H/D = 10%, the main flow is strongly affected by the Roughness at Reynolds number Re = 1,500. The Po number increases with Re and deviates from the prediction up to 11.9%. The Po number does not change a lot with S θ and S Z because D m almost keeps constant when the spacing is changed. For the rough microtubes with different R a values, the Po numbers can be almost the same, which prove that only with the R a value we can not determine the friction in the rough microtube. The mean value μ, the maximum and minimum values of the random Roughness are found to be critical to determine the Po number.
Jongwoon Park - One of the best experts on this subject based on the ideXlab platform.
-
investigation on slot die coating of hybrid material structure for oled lightings
Journal of Physics and Chemistry of Solids, 2016Co-Authors: Kwangjun Choi, Dongkyun Shin, Jongwoon ParkAbstract:Abstract With an attempt to fabricate large-area OLED lighting panels, we investigate slot-die coating of a small molecule (SM) hole transport layer (HTL). It is observed that SM HTL films formed by spin coating exhibit pinhole-like surface, whereas the films by slot-die coating show micro-sized hillocks due to agglomeration. As the plate temperature of the slot coater is increased, smaller hillocks appear more densely. To tackle it, a small amount of a polymer HTL is added into the SM HTL (Hybrid HTL). By the aid of entangled polymer chains, small molecules are prohibited from migrating and thus agglomerations disappear. The Peak-to-Peak Roughness of the slot-coated hybrid HTL films is measured to be about 11.5 nm, which is slightly higher than that (~7 nm) of the polymer HTL film, but much lower than that (~1071 nm) of the SM HTL film. Similar results are also observed in spin-coated films. It is also addressed that OLED with the hybrid HTL shows higher luminous efficacy, compared to OLED with the SM HTL or the polymer HTL. We have further demonstrated that the dissolution problem occurring between two stacked layers with different solvents during slot-die coating can be suppressed to a great extent using such a combination of materials in hybrid structure.
-
multilayer slot die coating of large area organic light emitting diodes
Organic Electronics, 2015Co-Authors: Kwangjun Choi, Jongwoon ParkAbstract:Abstract We investigate the slot-die coating process for the fabrication of large-area OLED lighting panels. Of many OLED layers, aqueous polymer-based hole injection layer (HIL) and small molecule-based hole transport layer (HTL) are formed using large-area slot-die coating. We are faced with three technical issues related with slot-die coating such as the flow down of an aqueous polymer solution near the inner perimeter of an insulator bank, pinhole-like surface in solution-processed small-molecule films, and the dissolution between two stacked layers with different solvents. We have suppressed those phenomena to a great extent and demonstrated that OLEDs with slot-die coated multiple layers show almost the same device performance as a reference OLED device with spin-coated HIL and vacuum-evaporated HTL. The Peak-to-Peak Roughness of the slot-die coated bilayer (HIL/HTL) films is observed to be less than 12.5 nm. The OLED device with the slot-die coated bilayer film exhibits the power efficiency of 27.2 lm/W at 1000 cd/m 2 , which is even higher than that (25.5 lm/W) of the reference device.
Renqiang Xiong - One of the best experts on this subject based on the ideXlab platform.
-
Investigation of laminar flow in microtubes with random rough surfaces
Microfluidics and Nanofluidics, 2009Co-Authors: Renqiang Xiong, J N ChungAbstract:A new approach of numerically generating a microtube with three-dimensional random surface Roughness is presented. In this approach, we combined a bi-cubic Coons patch with Gaussian distributed Roughness heights. Two random Roughness generation methods are studied. A computational fluid dynamic solver is used to solve the 3-D N–S equations for the flow through the generated rough microtubes with D = 50 μm and L = 100 μm. The effects of the Peak Roughness height, H , asperities spacing in the θ direction, S _ θ , and Z direction, S _ Z , standard deviation of the Gaussian distribution, σ , arithmetical mean Roughness, R _ a , on the Poiseuille number, Po are investigated. It is found that when H/D
-
Investigation of laminar flow in microtubes with random rough surfaces
Microfluidics and Nanofluidics, 2009Co-Authors: Renqiang Xiong, J N ChungAbstract:A new approach of numerically generating a microtube with three-dimensional random surface Roughness is presented. In this approach, we combined a bi-cubic Coons patch with Gaussian distributed Roughness heights. Two random Roughness generation methods are studied. A computational fluid dynamic solver is used to solve the 3-D N–S equations for the flow through the generated rough microtubes with D = 50 μm and L = 100 μm. The effects of the Peak Roughness height, H, asperities spacing in the θ direction, S θ , and Z direction, S Z , standard deviation of the Gaussian distribution, σ, arithmetical mean Roughness, R a, on the Poiseuille number, Po are investigated. It is found that when H/D < 5% the Po number can still be predicted by the conventional flow theory if the mean diameter of rough microtubes, D m, is used to be the hydraulic diameter D h. When H/D = 10%, the main flow is strongly affected by the Roughness at Reynolds number Re = 1,500. The Po number increases with Re and deviates from the prediction up to 11.9%. The Po number does not change a lot with S θ and S Z because D m almost keeps constant when the spacing is changed. For the rough microtubes with different R a values, the Po numbers can be almost the same, which prove that only with the R a value we can not determine the friction in the rough microtube. The mean value μ, the maximum and minimum values of the random Roughness are found to be critical to determine the Po number.
Kwangjun Choi - One of the best experts on this subject based on the ideXlab platform.
-
investigation on slot die coating of hybrid material structure for oled lightings
Journal of Physics and Chemistry of Solids, 2016Co-Authors: Kwangjun Choi, Dongkyun Shin, Jongwoon ParkAbstract:Abstract With an attempt to fabricate large-area OLED lighting panels, we investigate slot-die coating of a small molecule (SM) hole transport layer (HTL). It is observed that SM HTL films formed by spin coating exhibit pinhole-like surface, whereas the films by slot-die coating show micro-sized hillocks due to agglomeration. As the plate temperature of the slot coater is increased, smaller hillocks appear more densely. To tackle it, a small amount of a polymer HTL is added into the SM HTL (Hybrid HTL). By the aid of entangled polymer chains, small molecules are prohibited from migrating and thus agglomerations disappear. The Peak-to-Peak Roughness of the slot-coated hybrid HTL films is measured to be about 11.5 nm, which is slightly higher than that (~7 nm) of the polymer HTL film, but much lower than that (~1071 nm) of the SM HTL film. Similar results are also observed in spin-coated films. It is also addressed that OLED with the hybrid HTL shows higher luminous efficacy, compared to OLED with the SM HTL or the polymer HTL. We have further demonstrated that the dissolution problem occurring between two stacked layers with different solvents during slot-die coating can be suppressed to a great extent using such a combination of materials in hybrid structure.
-
multilayer slot die coating of large area organic light emitting diodes
Organic Electronics, 2015Co-Authors: Kwangjun Choi, Jongwoon ParkAbstract:Abstract We investigate the slot-die coating process for the fabrication of large-area OLED lighting panels. Of many OLED layers, aqueous polymer-based hole injection layer (HIL) and small molecule-based hole transport layer (HTL) are formed using large-area slot-die coating. We are faced with three technical issues related with slot-die coating such as the flow down of an aqueous polymer solution near the inner perimeter of an insulator bank, pinhole-like surface in solution-processed small-molecule films, and the dissolution between two stacked layers with different solvents. We have suppressed those phenomena to a great extent and demonstrated that OLEDs with slot-die coated multiple layers show almost the same device performance as a reference OLED device with spin-coated HIL and vacuum-evaporated HTL. The Peak-to-Peak Roughness of the slot-die coated bilayer (HIL/HTL) films is observed to be less than 12.5 nm. The OLED device with the slot-die coated bilayer film exhibits the power efficiency of 27.2 lm/W at 1000 cd/m 2 , which is even higher than that (25.5 lm/W) of the reference device.
Theresa S. Mayer - One of the best experts on this subject based on the ideXlab platform.
-
The Effect of Al0.7Ga0.3As Etch Stop Removal on the Preparation of Wafer‐Bonded Compliant Substrates
Journal of The Electrochemical Society, 1999Co-Authors: C. Zhang, D. Lubyshev, Thomas N. Jackson, David L. Miller, Theresa S. MayerAbstract:Preparation of GaAs-based compliant substrates that utilize wafer bonding generally relies on integrated Al x Ga 1- x As etch stop layers to provide the precise control required to stop selectively on GaAs layers less than 100 A thick. We demonstrate that removing an Al 0.7 Ga 0.3 As etch stop layer with HF or HCl:H 2 O leaves the underlying GaAs layers with rms Roughness of 10-20 A and Peak-to-Peak Roughness of 65-150 A. Following the Al 0.7 Ga 0.3 As selective etch, the morphology of the underlying GaAs layer is improved with a wet chemical digital etch comprised of alternate soaks in H 2 O 2 and HCl:H 2 O, which results in a GaAs surface with rms Roughness of ∼2 A and Peak-to-Peak Roughness of ∼20 A. Lattice-matched p + -n junctions deposited on thin-bonded GaAs substrates and test substrates that are prepared for growth using the digital etch have electrical characteristics comparable to those deposited on a bulk epi-ready GaAs substrates. However, similar lattice-mismatched In 0.2 Ga 0.8 As p + -n junctions deposited on the thin-bonded GaAs substrates and test substrates have dark currents that are more than an order of magnitude higher than those deposited on bulk epi-ready GaAs substrates. These results suggest that despite the smoothing of the digital etch, the material that remains on the surface of the thin GaAs layer is responsible for the degradation observed in the lattice-mismatched devices deposited on the thin-bonded GaAs substrates.
-
Demonstration of a GaAs-based compliant substrate using wafer bonding and substrate removal techniques
Compound Semiconductors 1997. Proceedings of the IEEE Twenty-Fourth International Symposium on Compound Semiconductors, 1997Co-Authors: C. Zhang, D. Lubyshev, W. Z. Cai, J. Neal, D. L. Miller, Theresa S. MayerAbstract:A GaAs-based compliant substrate that uses an intermediate AlGaAs-oxide layer to separate thin 150 /spl Aring/-1000 A GaAs compliant layers from a GaAs host substrate is described. The compliant substrates and epitaxial layers of lattice-mismatched In/sub 0.15/Ga/sub 0.85/As were studied using atomic force microscopy and double-crystal X-ray diffraction. The surface morphology of the 1000 A compliant substrate prior to growth had an RMS and Peak-to-Peak Roughness of 10 /spl Aring/ and 100 /spl Aring/. Following growth of 3000 /spl Aring/ In/sub 0.15/Ga/sub 0.85/ the root mean square (RMS) Roughness increased to 50 /spl Aring/, and slip lines were observed in the [110] direction. A comparison of lattice-matched p/sup +/-n junction diodes grown on a substrate with a 1000 /spl Aring/ compliant layer and a standard GaAs substrate revealed similar dark current-voltage characteristics, which demonstrate the high quality of the compliant substrate.