The Experts below are selected from a list of 33237 Experts worldwide ranked by ideXlab platform
Behzad Razavi - One of the best experts on this subject based on the ideXlab platform.
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Brief Papers_______________________________________________________________________________ Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits
2015Co-Authors: Jri Lee, Kenneth S Kundert, Behzad RazaviAbstract:Abstract—A large-signal piecewise-linear model is proposed for bang-bang Phase Detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander Phase detector and an LC oscillator. Index Terms—Bang-bang loops, binary PDs, CDR circuits, jitter, metastability, nonlinear Phase detector. I
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analysis and modeling of bang bang clock and data recovery circuits
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Kenneth S Kundert, Behzad RazaviAbstract:A large-signal piecewise-linear model is proposed for bang-bang Phase Detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander Phase detector and an LC oscillator.
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designing bangbang plls for clock and data recovery in serial data transmission systems
2003Co-Authors: Behzad RazaviAbstract:Clock recovery using Phase-locked loops (PLL) with binary (bang-bang) or ternary-quantized Phase Detectors has become increasingly common starting with the advent of fully monolithic clock and data recovery (CDR) Circuits in the late 1980's. Bang-bang CDR circuits have the unique advantages of inherent sampling Phase alignment, adaptability to multi-Phase sampling structures, and operation at the highest speed at which 8 process can make a working flip-flop. This paper gives insight into the behavior of the nonlinear bangbang PLL loop dynamics, giving approximate equations for loop jitter, recovered clock spectrum, and jitter tracking performance as a function of various design parameters. A novel analysis shows that the bang-bang loop output jitter grows as the square-root of the input jitter as contrasted with the linear dependence of the linear PLL.
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challenges in the design high speed clock and data recovery circuits
IEEE Communications Magazine, 2002Co-Authors: Behzad RazaviAbstract:This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of Phase detection for random data is addressed. Next, Hogge (1985), Alexander (1975), and half-rate Phase Detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.
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prospects of cmos technology for high speed optical communication circuits
IEEE Gallium Arsenide Integrated Circuit Symposium, 2001Co-Authors: Behzad RazaviAbstract:This paper explores the potential of CMOS technology for circuits operating at tens of gigahertz in an optical communications environment. An overview of modern CMOS processes is given and a generic optical system illustrating integration challenges is studied. The design of high-speed building blocks such as amplifiers, oscillators, and Phase Detectors is also described.
A Buzulutskov - One of the best experts on this subject based on the ideXlab platform.
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neutral bremsstrahlung and excimer electroluminescence in noble gases and its relevance to two Phase dark matter Detectors
arXiv: Instrumentation and Detectors, 2021Co-Authors: E Borisova, A BuzulutskovAbstract:Proportional electroluminescence (EL) is the physical effect used in two-Phase Detectors for dark matter searches, to optically record (in the gas Phase) the ionization signal produced by particle scattering in the liquid Phase. In our previous work the presence of a new EL mechanism, namely that of neutral bremsstrahlung (NBrS), was demonstrated in two-Phase argon Detectors both theoretically and experimentally, in addition to the ordinary EL mechanism due to excimer emission. In this work the similar theoretical approach is applied to all noble gases, i.e. overall to helium, neon, argon, krypton and xenon, to calculate the EL yields and spectra both for NBrS and excimer EL. The relevance of the results obtained to the development of two-Phase dark matter Detectors is discussed.
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revealing neutral bremsstrahlung in two Phase argon electroluminescence
Astroparticle Physics, 2018Co-Authors: A Buzulutskov, A Bondar, E Shemyakina, A D Dolgov, E N Frolov, V NosovAbstract:Abstract Proportional electroluminescence (EL) in noble gases has long been used in two-Phase Detectors for dark matter search, to record ionization signals induced by particle scattering in the noble-gas liquid (S2 signals). Until recently, it was believed that proportional electroluminescence was fully due to VUV emission of noble gas excimers produced in atomic collisions with excited atoms, the latter being in turn produced by drifting electrons. In this work we consider an additional mechanism of proportional electroluminescence, namely that of bremsstrahlung of drifting electrons scattered on neutral atoms (so-called neutral bremsstrahlung); it is systemically studied here both theoretically and experimentally. In particular, the absolute EL yield has for the first time been measured in pure gaseous argon in the two-Phase mode, using a dedicated two-Phase detector with EL gap optically read out by cryogenic PMTs and SiPMs. We show that the neutral bremsstrahlung effect can explain two intriguing observations in EL radiation: that of the substantial contribution of the non-VUV spectral component, extending from the UV to NIR, and that of the photon emission at lower electric fields, below the Ar excitation threshold. Possible applications of neutral bremsstrahlung effect in two-Phase dark matter Detectors are discussed.
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two Phase argon and xenon avalanche Detectors based on gas electron multipliers
Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 2006Co-Authors: A Bondar, A Buzulutskov, A A Grebenuk, D Pavlyuchenko, R Snopkov, Y A TikhonovAbstract:Abstract We study the performance of two-Phase avalanche Detectors based on Gas Electron Multipliers (GEMs) and operated in an electron-avalanching mode in Ar and Xe. Emission, gain, energy resolution and stability characteristics of the Detectors were studied. Rather high gains, reaching 5000, and stable operation for several hours were observed in the two-Phase Ar avalanche detector using a triple-GEM multiplier. The signals induced by X-rays, β -particles and γ-rays were successfully recorded. Preliminary results were obtained in the two-Phase Xe avalanche detector: the maximum gain of the triple-GEM in two-Phase Xe and Xe+2%CH 4 was about 200. The results obtained are relevant in the field of two-Phase Detectors for dark matter searches, coherent neutrino scattering, PET and digital radiography.
A A Abidi - One of the best experts on this subject based on the ideXlab platform.
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design methodology for Phase locked loops using binary bang bang Phase Detectors
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: A A AbidiAbstract:We present a linearized analysis of bang-bang Phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output Phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps to answer long-standing questions on aspects of these circuits attributable a hard nonlinearity. A brief designer’s guide is included.
Carlo Samori - One of the best experts on this subject based on the ideXlab platform.
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analysis and design of low jitter digital bang bang Phase locked loops
IEEE Transactions on Circuits and Systems, 2014Co-Authors: Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo SamoriAbstract:Digital Phase-locked loops based on bang-bang Phase Detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of Phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both Phase detector and DCO, and the Phase noise of DCO, with both 1/f 2 and 1/f 3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.
Kenneth S Kundert - One of the best experts on this subject based on the ideXlab platform.
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Brief Papers_______________________________________________________________________________ Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits
2015Co-Authors: Jri Lee, Kenneth S Kundert, Behzad RazaviAbstract:Abstract—A large-signal piecewise-linear model is proposed for bang-bang Phase Detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander Phase detector and an LC oscillator. Index Terms—Bang-bang loops, binary PDs, CDR circuits, jitter, metastability, nonlinear Phase detector. I
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analysis and modeling of bang bang clock and data recovery circuits
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Kenneth S Kundert, Behzad RazaviAbstract:A large-signal piecewise-linear model is proposed for bang-bang Phase Detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander Phase detector and an LC oscillator.
