The Experts below are selected from a list of 12486 Experts worldwide ranked by ideXlab platform
Hong-june Park - One of the best experts on this subject based on the ideXlab platform.
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ISOCC - All-synthesizable transmitter driver and Data Recovery circuit for USB2.0 interface
2016 International SoC Design Conference (ISOCC), 2016Co-Authors: Kihwan Seong, Hong-june ParkAbstract:The transmitter driver and the Data Recovery circuit of receiver for 480 Mbps USB2.0 interface were designed with Verilog and synthesized to enhance design portability. The transmitter driver was implemented by using multiple tri-state inverter cells to generate a 0 ∼ 400 mV swing for normal operation and a 0 ∼ 800 mV swing for chirp operation. The Data Recovery circuit was implemented by using a blind over-sampling method with 5-phase 480 MHz clocks. The proposed transmitter driver and Data Recovery circuits were fabricated in a 65 nm CMOS process; the transmitter driver satisfies the USB2.0 eye-mask specification in the measured eye diagrams and the Data Recovery circuits gives a measured BER less than 1E-12 with PRBS 2E31-1 Data and a USB2.0 5m cable. The transmitter driver and the Data Recovery circuit consume 24.3 mW and 1.6 mW, respectively at 1.2 V supply.
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All-synthesizable transmitter driver and Data Recovery circuit for USB2.0 interface
2016 International SoC Design Conference (ISOCC), 2016Co-Authors: Kihwan Seong, Hong-june ParkAbstract:The transmitter driver and the Data Recovery circuit of receiver for 480 Mbps USB2.0 interface were designed with Verilog and synthesized to enhance design portability. The transmitter driver was implemented by using multiple tri-state inverter cells to generate a 0 ~ 400 mV swing for normal operation and a 0 ~ 800 mV swing for chirp operation. The Data Recovery circuit was implemented by using a blind over-sampling method with 5-phase 480 MHz clocks. The proposed transmitter driver and Data Recovery circuits were fabricated in a 65 nm CMOS process; the transmitter driver satisfies the USB2.0 eye-mask specification in the measured eye diagrams and the Data Recovery circuits gives a measured BER less than 1E-12 with PRBS 2E31-1 Data and a USB2.0 5m cable. The transmitter driver and the Data Recovery circuit consume 24.3 mW and 1.6 mW, respectively at 1.2 V supply.
Kihwan Seong - One of the best experts on this subject based on the ideXlab platform.
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ISOCC - All-synthesizable transmitter driver and Data Recovery circuit for USB2.0 interface
2016 International SoC Design Conference (ISOCC), 2016Co-Authors: Kihwan Seong, Hong-june ParkAbstract:The transmitter driver and the Data Recovery circuit of receiver for 480 Mbps USB2.0 interface were designed with Verilog and synthesized to enhance design portability. The transmitter driver was implemented by using multiple tri-state inverter cells to generate a 0 ∼ 400 mV swing for normal operation and a 0 ∼ 800 mV swing for chirp operation. The Data Recovery circuit was implemented by using a blind over-sampling method with 5-phase 480 MHz clocks. The proposed transmitter driver and Data Recovery circuits were fabricated in a 65 nm CMOS process; the transmitter driver satisfies the USB2.0 eye-mask specification in the measured eye diagrams and the Data Recovery circuits gives a measured BER less than 1E-12 with PRBS 2E31-1 Data and a USB2.0 5m cable. The transmitter driver and the Data Recovery circuit consume 24.3 mW and 1.6 mW, respectively at 1.2 V supply.
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All-synthesizable transmitter driver and Data Recovery circuit for USB2.0 interface
2016 International SoC Design Conference (ISOCC), 2016Co-Authors: Kihwan Seong, Hong-june ParkAbstract:The transmitter driver and the Data Recovery circuit of receiver for 480 Mbps USB2.0 interface were designed with Verilog and synthesized to enhance design portability. The transmitter driver was implemented by using multiple tri-state inverter cells to generate a 0 ~ 400 mV swing for normal operation and a 0 ~ 800 mV swing for chirp operation. The Data Recovery circuit was implemented by using a blind over-sampling method with 5-phase 480 MHz clocks. The proposed transmitter driver and Data Recovery circuits were fabricated in a 65 nm CMOS process; the transmitter driver satisfies the USB2.0 eye-mask specification in the measured eye diagrams and the Data Recovery circuits gives a measured BER less than 1E-12 with PRBS 2E31-1 Data and a USB2.0 5m cable. The transmitter driver and the Data Recovery circuit consume 24.3 mW and 1.6 mW, respectively at 1.2 V supply.
Behzad Razavi - One of the best experts on this subject based on the ideXlab platform.
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Optimization of PhaseLocked Loop Performance in Data Recovery Systems
Monolithic Phase-Locked Loops and Clock Recovery Circuits, 2020Co-Authors: Behzad RazaviAbstract:Optimized design conditions are presented for a phase-locked loop (PLL) used as a functional block in Data Recovery systems with the primary function of timing Recovery. A mathematical model is presented which takes into account the nonlinear and discrete-time nature of the PLL when used in Data Recovery applications. Performance attributes for these systems such as acquisition, tracking, and noise are considered. A systematic design procedure is presented which permits quantitative trade-otis among these performance attributes. The validation of the mathematical model and the systematic design procedure on a practical circuit implementation in CMOS technology is described.
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challenges in the design high speed clock and Data Recovery circuits
IEEE Communications Magazine, 2002Co-Authors: Behzad RazaviAbstract:This article describes the challenges in the design of monolithic clock and Data Recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random Data is addressed. Next, Hogge (1985), Alexander (1975), and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and Data Recovery architectures are presented.
Unku Moon - One of the best experts on this subject based on the ideXlab platform.
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a wide tracking range clock and Data Recovery circuit
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Pavan Kumar Hanumolu, Unku MoonAbstract:A hybrid analog-digital quarter-rate clock and Data Recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate Data Recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER <10-12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.
Bernard Shibwabo Kasamani - One of the best experts on this subject based on the ideXlab platform.
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Intelli-restore as an instantaneous approach for reduced Data Recovery time
Journal of Systems Integration, 2012Co-Authors: Leon Mugoh, Ismail Lukandu Ateya, Bernard Shibwabo KasamaniAbstract:Due to the competitive and regulatory pressures and the high demands and dependence placed on Data, there is need for higher Data availability and a faster means of recovering the Data in case it becomes corrupted or lost. Based on results provided on the reasons behind the long / high Data Recovery times by Kenyan SMEs this paper provides a solution that reduces the Data Recovery time. In order to solve the problem of high Data Recovery times, an instantaneous Data Recovery strategy based on an existing Continuous Data Protection (CDP) architecture is introduced as an important component of a well-rounded backup and Recovery strategy. CDP is a disk based backup solution which ensures that Data is retrieved at a much faster rate during Recovery. The solution presented in this paper could help organizations adopt or complement existing Data Recovery strategies.
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Continuous Data Protection as a Strategy for Reduced Data Recovery Time
Journal of Systems Integration, 2011Co-Authors: Leon Mugoh, Ismail Lukandu Ateya, Bernard Shibwabo KasamaniAbstract:This paper presents the reasons behind the long / high Data Recovery times by Kenyan Firms and provides a solution that reduces the Data backup for Recovery time. It was found that the time taken to recover Data was reasonably high because of the type of media that was used for backing up Data: the magnetic Data tape. In order to solve the problem of high Data Recovery times, Continuous Data Protection (CDP) is introduced as an important component of a well-rounded backup and Recovery strategy to complement the existing backup strategy as CDP is a disk based backup solution which ensures that Data is retrieved at a much faster rate. The findings presented in this paper could help researchers design a strategy for instanteneous Data Recovery based on Continuous Data protection.
