The Experts below are selected from a list of 12711 Experts worldwide ranked by ideXlab platform
Renner Renato - One of the best experts on this subject based on the ideXlab platform.
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Fundamental Energy Requirement of Reversible Quantum Operations
'American Physical Society (APS)', 2021Co-Authors: Chiribella Giulio, Yang Yuxiang, Renner RenatoAbstract:Landauer’s principle asserts that any computation has an unavoidable energy cost that grows proportionally to its degree of logical irreversibility. But even a logically reversible operation, when run on a Physical Processor that operates on different energy levels, requires energy. Here we quantify this energy requirement, providing upper and lower bounds that coincide up to a constant factor. We derive these bounds from a general quantum resource-theoretic argument, which implies that the initial resource requirement for implementing a unitary operation within an error ε grows like 1/√ε times the amount of resource generated by the operation. Applying these results to quantum circuits, we find that their energy requirement can, by an appropriate design, be made independent of their time complexity.ISSN:2160-330
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Fundamental energy requirement of reversible quantum operations
'American Physical Society (APS)', 2021Co-Authors: Chiribella Giulio, Yang Yuxiang, Renner RenatoAbstract:Landauer's principle asserts that any computation has an unavoidable energy cost that grows proportionally to its degree of logical irreversibility. But even a logically reversible operation, when run on a Physical Processor that operates on different energy levels, requires energy. Here we quantify this energy requirement, providing upper and lower bounds that coincide up to a constant factor. We derive these bounds from a general quantum resource-theoretic argument, which implies that the initial resource requirement for implementing a unitary operation within an error~$\epsilon$ grows like $1/\sqrt \epsilon$ times the amount of resource generated by the operation. Applying these results to quantum circuits, we find that their energy requirement can, by an appropriate design, be made independent of their time complexity.Comment: 6 pages + appendix, 3 figures; close to published versio
Hyonsoo Lee - One of the best experts on this subject based on the ideXlab platform.
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a programmable digital neuro Processor design with dynamically reconfigurable pipeline parallel architecture
International Conference on Parallel and Distributed Systems, 1998Co-Authors: Youngjin Jang, Chan Ho Park, Hyonsoo LeeAbstract:Previous neural network Processors were configured either into a SIMD or into an instruction systolic array (ISA) ring architecture using the canonical mapping methodology. The disadvantages of these Processors are the lack of generality, scalability, programmability and reconfigurability. So, we propose a programmable neuroProcessor whose architecture is dynamically reconfigurable into either SIMD or an ISA ring according to the data dependencies of any neural network model. To improve the computing time, the computation of an activation function, which typically needed tens of cycles in previous Processors, can be done in a single cycle by using piecewise linear (PWL) function approximation. Using a simple bus architecture and instruction set, the proposed Processor allows the implementation of neural networks larger than the Physical Processor element array and allows the user to solve any neural network model. We verify these properties with the error backpropagation (EBP) model and estimate the computation time of the proposed Processor.
Chiribella Giulio - One of the best experts on this subject based on the ideXlab platform.
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Fundamental Energy Requirement of Reversible Quantum Operations
'American Physical Society (APS)', 2021Co-Authors: Chiribella Giulio, Yang Yuxiang, Renner RenatoAbstract:Landauer’s principle asserts that any computation has an unavoidable energy cost that grows proportionally to its degree of logical irreversibility. But even a logically reversible operation, when run on a Physical Processor that operates on different energy levels, requires energy. Here we quantify this energy requirement, providing upper and lower bounds that coincide up to a constant factor. We derive these bounds from a general quantum resource-theoretic argument, which implies that the initial resource requirement for implementing a unitary operation within an error ε grows like 1/√ε times the amount of resource generated by the operation. Applying these results to quantum circuits, we find that their energy requirement can, by an appropriate design, be made independent of their time complexity.ISSN:2160-330
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Fundamental energy requirement of reversible quantum operations
'American Physical Society (APS)', 2021Co-Authors: Chiribella Giulio, Yang Yuxiang, Renner RenatoAbstract:Landauer's principle asserts that any computation has an unavoidable energy cost that grows proportionally to its degree of logical irreversibility. But even a logically reversible operation, when run on a Physical Processor that operates on different energy levels, requires energy. Here we quantify this energy requirement, providing upper and lower bounds that coincide up to a constant factor. We derive these bounds from a general quantum resource-theoretic argument, which implies that the initial resource requirement for implementing a unitary operation within an error~$\epsilon$ grows like $1/\sqrt \epsilon$ times the amount of resource generated by the operation. Applying these results to quantum circuits, we find that their energy requirement can, by an appropriate design, be made independent of their time complexity.Comment: 6 pages + appendix, 3 figures; close to published versio
Youngjin Jang - One of the best experts on this subject based on the ideXlab platform.
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a programmable digital neuro Processor design with dynamically reconfigurable pipeline parallel architecture
International Conference on Parallel and Distributed Systems, 1998Co-Authors: Youngjin Jang, Chan Ho Park, Hyonsoo LeeAbstract:Previous neural network Processors were configured either into a SIMD or into an instruction systolic array (ISA) ring architecture using the canonical mapping methodology. The disadvantages of these Processors are the lack of generality, scalability, programmability and reconfigurability. So, we propose a programmable neuroProcessor whose architecture is dynamically reconfigurable into either SIMD or an ISA ring according to the data dependencies of any neural network model. To improve the computing time, the computation of an activation function, which typically needed tens of cycles in previous Processors, can be done in a single cycle by using piecewise linear (PWL) function approximation. Using a simple bus architecture and instruction set, the proposed Processor allows the implementation of neural networks larger than the Physical Processor element array and allows the user to solve any neural network model. We verify these properties with the error backpropagation (EBP) model and estimate the computation time of the proposed Processor.
Sangman Moh - One of the best experts on this subject based on the ideXlab platform.
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adjacency based mapping of mesh processes for switch based cluster systems of irregular topology
Journal of the Institute of Electronics Engineers of Korea, 2010Co-Authors: Sangman MohAbstract:Mapping virtual process topology to Physical Processor topology is one of the most important design issues in parallel programming. However, the mapping problem is complicated due to the topology irregularity and routing complexity. This paper proposes a new process mapping scheme called adjacency-based mapping (AM) for irregular cluster systems assuming that the two-dimensional mesh process topology is specified as an interprocess communication pattern. The cluster systems have been studied and developed for many years since they provide high interconnection flexibility, scalability, and expandability which are not attainable in traditional regular networks. The proposed AM tries to map neighboring processes in virtual process topology to adjacent Processors in Physical Processor topology. Simulation study shows that the proposed AM results in better mapping quality and shorter interprocess latency compared to the conventional approaches.
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adjacency based mesh process mapping for irregular cluster systems
High Performance Computing and Communications, 2009Co-Authors: Sangman MohAbstract:This paper proposes a new process mapping scheme called adjacency-based mapping (AM) for irregular cluster systems assuming that the two-dimensional mesh process topology is specified as an interprocess communication pattern. The proposed AM tries to map neighboring processes in virtual process topology to adjacent Processors in Physical Processor topology. Simulation study shows that the proposed AM results in better mapping quality and shorter interprocess latency compared to the conventional approaches.
