The Experts below are selected from a list of 276 Experts worldwide ranked by ideXlab platform

Florin Udrea - One of the best experts on this subject based on the ideXlab platform.

  • 200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics
    IEEE Transactions on Electron Devices, 2013
    Co-Authors: Marina Antoniou, Steven John Pilkington, Alexander Holke, Florin Udrea, Wan Azlan Bin Wan Zainal Abidin
    Abstract:

    This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar Transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong Pnp Transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 A/cm2. The latch-up current density is 1100 A/cm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A/cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area.

  • An on-state analytical model for the Trench Insulated Gate Bipolar Transistor (TIGBT)
    Solid-State Electronics, 1997
    Co-Authors: Florin Udrea, Gehan A. J. Amaratunga
    Abstract:

    Abstract A specific, physically-based analytical model for the Trench Insulated Gate Bipolar Transistor which accounts for a combined PIN diode- Pnp Transistor carrier dynamics is proposed. Previous models (i.e. PIN model and Pnp Transistor model) cannot account properly for the carrier distribution in Trench IGBT since neither the Pnp Transistor nor the PIN diode effect can be neglected. The physics of the Trench IGBT based on a parallel and coupled PIN diode- Pnp Transistor action is accurately described using numerical simulations and analytical modeling. An optimised Trench IGBT with an enhanced PIN diode effect has substantially improved on-state characteristics and is potentially the most attractive device in the area of high voltage fast switching devices.

  • A steady-state analytical model for the trench insulated gate bipolar Transistor
    1995 International Semiconductor Conference. CAS '95 Proceedings, 1
    Co-Authors: Florin Udrea, Gehan A. J. Amaratunga
    Abstract:

    A steady-state, physically-based analytical model for the trench Insulated Gate Bipolar Transistor (IGBT) which accounts for a combined PIN diode-Pnp Transistor carrier dynamics is proposed. Previous models (i.e. PIN model and Pnp Transistor model) cannot account properly for the carrier dynamics in trench IGBT since neither the Pnp Transistor nor the PIN diode effect can be neglected. An optimised trench IGBT with a large ratio between the accumulation layer and the cell size leads to substantially improved on-state characteristics, which makes the trench IGBT potentially the most attractive device in the area of high voltage fast switching devices.

Bosco Leung - One of the best experts on this subject based on the ideXlab platform.

  • A class-AB high-speed low-power operational amplifier in BiCMOS technology
    IEEE Journal of Solid-State Circuits, 1996
    Co-Authors: Subhajit Sen, Bosco Leung
    Abstract:

    A BiCMOS op-amp is described which exploits BiCMOS technology to obtain very high transconductance, slew-rate, and fast small-signal-settling response. The absence of vertical Pnp Transistor requires the op-amp to use a wideband, composite PMOS-vertical-NPN structure as a substitute for Pnp Transistors to realize a class-AB input stage of an op-amp. The AC small-signal equivalent circuit of the input stage is analyzed and methods for optimizing the nondominant pole positions to obtain fast settling are given. Measurements in the unity-gain buffer configuration indicate maximum slew-rates of 150 V//spl mu/s (rising) and 280 V//spl mu/s (falling) and a transconductance of 20 mS at a quiescent power of 20 mW from 5 V supply using a 0.8-/spl mu/m BiCMOS process with peak f/sub T/ of 11 GHz.

  • ISCAS - A low-power class-AB BiCMOS opamp using 'pseudo-Pnp' Transistors
    1993 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: S. Sen, Bosco Leung
    Abstract:

    A low-power Class AB BiCMOS operational amplifier is discussed. Low power is achieved through Class-AB architecture, as well as through a structure called pseudo-Pnp. The pseudo-Pnp structure, along with an appropriate level-shifting arrangement, has the advantages of high transconductance per unit of bias current and zero input bias current as compared to either a PMOS or a lateral-Pnp Transistor. The application, advantages and tradeoffs of this structure as input devices and current-mirrors, are explained. A Class-AB operational amplifier using pseudo-Pnp is proposed. For 0.8-/spl mu/m BiCMOS technology, this shows a gain of 73.8 dB, a unity gain bandwidth of 49 MHz, and a settling time of 98 ns for a 2.5 V step at a quiescent power of 12 mW. >

Wan Azlan Bin Wan Zainal Abidin - One of the best experts on this subject based on the ideXlab platform.

  • 200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics
    IEEE Transactions on Electron Devices, 2013
    Co-Authors: Marina Antoniou, Steven John Pilkington, Alexander Holke, Florin Udrea, Wan Azlan Bin Wan Zainal Abidin
    Abstract:

    This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar Transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong Pnp Transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 A/cm2. The latch-up current density is 1100 A/cm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A/cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area.

T. Nakamura - One of the best experts on this subject based on the ideXlab platform.

  • Self-aligned complementary bipolar technology for low-power dissipation and ultra-high-speed LSIs
    IEEE Transactions on Electron Devices, 1995
    Co-Authors: Takahiro Onai, Eiji Ohue, Y. Idei, Masamichi Tanabe, Hiromi Shimamoto, Katsuyoshi Washio, T. Nakamura
    Abstract:

    Fully symmetrical complementary bipolar Transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-/spl mu/m SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the Pnp Transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and Pnp Transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and Pnp Transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit. >

  • An NPN 30 GHz, Pnp 32 GHz f/sub T/ complementary bipolar technology
    Proceedings of IEEE International Electron Devices Meeting, 1
    Co-Authors: Takahiro Onai, Eiji Ohue, Y. Idei, Masamichi Tanabe, Hiromi Shimamoto, Katsuyoshi Washio, T. Nakamura
    Abstract:

    Fully symmetrical complementary bipolar Transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-/spl mu/m SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of boron diffusion layer suppressed upward diffusion of boron in the subcollector of the Pnp Transistor during epitaxial growth. This enabled thin epitaxial layer growth of both npn and Pnp Transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and Pnp Transistors, respectively. These results showed that the power dissipation is reduced to 1/4 in a complementary active pulldown circuit compared with an ECL circuit. >

Gehan A. J. Amaratunga - One of the best experts on this subject based on the ideXlab platform.

  • An on-state analytical model for the Trench Insulated Gate Bipolar Transistor (TIGBT)
    Solid-State Electronics, 1997
    Co-Authors: Florin Udrea, Gehan A. J. Amaratunga
    Abstract:

    Abstract A specific, physically-based analytical model for the Trench Insulated Gate Bipolar Transistor which accounts for a combined PIN diode- Pnp Transistor carrier dynamics is proposed. Previous models (i.e. PIN model and Pnp Transistor model) cannot account properly for the carrier distribution in Trench IGBT since neither the Pnp Transistor nor the PIN diode effect can be neglected. The physics of the Trench IGBT based on a parallel and coupled PIN diode- Pnp Transistor action is accurately described using numerical simulations and analytical modeling. An optimised Trench IGBT with an enhanced PIN diode effect has substantially improved on-state characteristics and is potentially the most attractive device in the area of high voltage fast switching devices.

  • A steady-state analytical model for the trench insulated gate bipolar Transistor
    1995 International Semiconductor Conference. CAS '95 Proceedings, 1
    Co-Authors: Florin Udrea, Gehan A. J. Amaratunga
    Abstract:

    A steady-state, physically-based analytical model for the trench Insulated Gate Bipolar Transistor (IGBT) which accounts for a combined PIN diode-Pnp Transistor carrier dynamics is proposed. Previous models (i.e. PIN model and Pnp Transistor model) cannot account properly for the carrier dynamics in trench IGBT since neither the Pnp Transistor nor the PIN diode effect can be neglected. An optimised trench IGBT with a large ratio between the accumulation layer and the cell size leads to substantially improved on-state characteristics, which makes the trench IGBT potentially the most attractive device in the area of high voltage fast switching devices.