The Experts below are selected from a list of 221766 Experts worldwide ranked by ideXlab platform
Yiming Wang - One of the best experts on this subject based on the ideXlab platform.
-
a duty cycle distortion tolerant half delay line low Power fast lock in all digital delay locked loop
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Jinnshyan Wang, Chunyuan Cheng, Jeching Liu, Yuchia Liu, Yiming WangAbstract:This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low Power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ?W/MHz Power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.
Yulin Zhang - One of the best experts on this subject based on the ideXlab platform.
-
frontal eeg asymmetry and middle line Power Difference in discrete emotions
Frontiers in Behavioral Neuroscience, 2018Co-Authors: Guozhen Zhao, Yulin ZhangAbstract:A traditional model of emotion cannot explain the Differences in brain activities between two discrete emotions that are similar in the valence-arousal coordinate space. The current study elicited two positive emotions (amusement and tenderness) and two negative emotions (anger and fear) that are similar in both valence and arousal dimensions to examine the Differences in brain activities in these emotional states. Frontal electroencephalographic (EEG) asymmetry and midline Power in three bands (theta, alpha, and beta) were measured when participants watched affective film excerpts. Significant Differences were detected between tenderness and amusement on FP1/FP2 theta asymmetry, F3/F4 theta and alpha asymmetry. Significant Differences between anger and fear on FP1/FP2 theta asymmetry and F3/F4 alpha asymmetry were also observed. For midline Power, midline theta Power could distinguish two negative emotions, while midline alpha and beta Power could effectively differentiate two positive emotions. Liking and dominance were also related to EEG features. Stepwise multiple linear regression results revealed that frontal alpha and theta asymmetry could predict the subjective feelings of two positive and two negative emotions in different patterns. The binary classification accuracy, which used EEG frontal asymmetry and midline Power as features and SVM as classifiers, was as high as 64.52% for tenderness and amusement and 78.79% for anger and fear. The classification accuracy was improved after adding these features to other features extracted across the scalp. These findings indicate that frontal EEG asymmetry and midline Power might have the potential to recognize discrete emotions that are similar in the valence-arousal coordinate space.
-
frontal eeg asymmetry and middle line Power Difference in discrete emotions
Frontiers in Behavioral Neuroscience, 2018Co-Authors: Guozhen Zhao, Yulin ZhangAbstract:A traditional model of emotion cannot explain the Differences in brain activities between two discrete emotions that are similar in the valence-arousal coordinate space. The current study elicited two positive emotions (amusement and tenderness) and two negative emotions (anger and fear) that are similar in both valence and arousal dimensions to examine the Differences in brain activities in these emotional states. Frontal electroencephalographic (EEG) asymmetry and midline Power in three bands (theta, alpha and beta) were measured when participants watched affective film excerpts. Significant Differences were detected between tenderness and amusement on FP1/FP2 theta asymmetry, F3/F4 theta and alpha asymmetry. Significant Differences between anger and fear on FP1/FP2 theta asymmetry and F3/F4 alpha asymmetry were also observed. For midline Power, midline theta Power could distinguish two negative emotions, while midline alpha and beta Power could effectively differentiate two positive emotions. Liking and dominance were also related to EEG features. Stepwise multiple linear regression results revealed that frontal alpha and theta asymmetry could predict the subjective feelings of two positive and two negative emotions in different patterns. The binary classification accuracy, which used EEG frontal asymmetry and midline Power as features and support vector machine (SVM) as classifiers, was as high as 64.52% for tenderness and amusement and 78.79% for anger and fear. The classification accuracy was improved after adding these features to other features extracted across the scalp. These findings indicate that frontal EEG asymmetry and midline Power might have the potential to recognize discrete emotions that are similar in the valence-arousal coordinate space.
Jinnshyan Wang - One of the best experts on this subject based on the ideXlab platform.
-
a duty cycle distortion tolerant half delay line low Power fast lock in all digital delay locked loop
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Jinnshyan Wang, Chunyuan Cheng, Jeching Liu, Yuchia Liu, Yiming WangAbstract:This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low Power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ?W/MHz Power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.
Chunyuan Cheng - One of the best experts on this subject based on the ideXlab platform.
-
a duty cycle distortion tolerant half delay line low Power fast lock in all digital delay locked loop
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Jinnshyan Wang, Chunyuan Cheng, Jeching Liu, Yuchia Liu, Yiming WangAbstract:This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low Power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ?W/MHz Power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.
Jeching Liu - One of the best experts on this subject based on the ideXlab platform.
-
a duty cycle distortion tolerant half delay line low Power fast lock in all digital delay locked loop
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Jinnshyan Wang, Chunyuan Cheng, Jeching Liu, Yuchia Liu, Yiming WangAbstract:This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low Power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ?W/MHz Power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.