The Experts below are selected from a list of 327 Experts worldwide ranked by ideXlab platform

Jin Wang - One of the best experts on this subject based on the ideXlab platform.

  • High voltage SiC super-cascode Power Switch parameter optimization for loss reduction
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 2018
    Co-Authors: He Li, Boxue Hu, Jin Wang
    Abstract:

    A method for voltage balancing capacitor selection of high voltage silicon carbide (SiC) Junction Gate Field Effect Transistor (JEFTs) based super-cascode Power Switch (SCPS) is presented in this paper. The proposed method can effectively reduce the device Switching loss as well as thermal stress on critical components caused by repetitive avalanche. The basic operation principle of SCPS is shown at the beginning of the paper with critical modes. Then, equations to describe the voltage distribution among all the SiC JEFTs have been derived. Based on the derived equations, a sizing method of the SCPS voltage balancing capacitors is proposed to accelerate the device Switching speed and minimize the avalanche time of its internal diodes. Compared with no voltage balancing capacitor case, the turn-on loss of the SCPS with sized capacitors has been reduced to 9.7%. The turn-off loss has been reduced to 48.4%.

  • Optimization Method to Eliminate Turn-on Overvoltage Issue of the High Voltage SiC Super-Cascode Power Switch
    2018 IEEE 4th Southern Power Electronics Conference (SPEC), 2018
    Co-Authors: He Li, Boxue Hu, Jin Wang
    Abstract:

    A potential overvoltage issue during turn-on transient of the silicon carbide (SiC) junction gate field-effect transistor (JFET) based high voltage super-cascode Power Switch (SCPS) is first identified. The overvoltage issue caused by the JFET slow sequential turn-on is investigated, and the corresponding mitigation method is proposed. Based on this, an optimization method is proposed to improve JFET voltage balancing during off-state as well as eliminating the overvoltage during turn-on transient in the high voltage SiC super-cascode structure. The analysis is verified with experimental results. The overvoltage on the top JFET is eliminated and the total turn-on time is reduced from 518 ns to 82 ns. In the end, the influence of the voltage balancing capacitor tolerance on the voltage distribution is discussed.

He Li - One of the best experts on this subject based on the ideXlab platform.

  • High voltage SiC super-cascode Power Switch parameter optimization for loss reduction
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 2018
    Co-Authors: He Li, Boxue Hu, Jin Wang
    Abstract:

    A method for voltage balancing capacitor selection of high voltage silicon carbide (SiC) Junction Gate Field Effect Transistor (JEFTs) based super-cascode Power Switch (SCPS) is presented in this paper. The proposed method can effectively reduce the device Switching loss as well as thermal stress on critical components caused by repetitive avalanche. The basic operation principle of SCPS is shown at the beginning of the paper with critical modes. Then, equations to describe the voltage distribution among all the SiC JEFTs have been derived. Based on the derived equations, a sizing method of the SCPS voltage balancing capacitors is proposed to accelerate the device Switching speed and minimize the avalanche time of its internal diodes. Compared with no voltage balancing capacitor case, the turn-on loss of the SCPS with sized capacitors has been reduced to 9.7%. The turn-off loss has been reduced to 48.4%.

  • Optimization Method to Eliminate Turn-on Overvoltage Issue of the High Voltage SiC Super-Cascode Power Switch
    2018 IEEE 4th Southern Power Electronics Conference (SPEC), 2018
    Co-Authors: He Li, Boxue Hu, Jin Wang
    Abstract:

    A potential overvoltage issue during turn-on transient of the silicon carbide (SiC) junction gate field-effect transistor (JFET) based high voltage super-cascode Power Switch (SCPS) is first identified. The overvoltage issue caused by the JFET slow sequential turn-on is investigated, and the corresponding mitigation method is proposed. Based on this, an optimization method is proposed to improve JFET voltage balancing during off-state as well as eliminating the overvoltage during turn-on transient in the high voltage SiC super-cascode structure. The analysis is verified with experimental results. The overvoltage on the top JFET is eliminated and the total turn-on time is reduced from 518 ns to 82 ns. In the end, the influence of the voltage balancing capacitor tolerance on the voltage distribution is discussed.

Boxue Hu - One of the best experts on this subject based on the ideXlab platform.

  • High voltage SiC super-cascode Power Switch parameter optimization for loss reduction
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 2018
    Co-Authors: He Li, Boxue Hu, Jin Wang
    Abstract:

    A method for voltage balancing capacitor selection of high voltage silicon carbide (SiC) Junction Gate Field Effect Transistor (JEFTs) based super-cascode Power Switch (SCPS) is presented in this paper. The proposed method can effectively reduce the device Switching loss as well as thermal stress on critical components caused by repetitive avalanche. The basic operation principle of SCPS is shown at the beginning of the paper with critical modes. Then, equations to describe the voltage distribution among all the SiC JEFTs have been derived. Based on the derived equations, a sizing method of the SCPS voltage balancing capacitors is proposed to accelerate the device Switching speed and minimize the avalanche time of its internal diodes. Compared with no voltage balancing capacitor case, the turn-on loss of the SCPS with sized capacitors has been reduced to 9.7%. The turn-off loss has been reduced to 48.4%.

  • Optimization Method to Eliminate Turn-on Overvoltage Issue of the High Voltage SiC Super-Cascode Power Switch
    2018 IEEE 4th Southern Power Electronics Conference (SPEC), 2018
    Co-Authors: He Li, Boxue Hu, Jin Wang
    Abstract:

    A potential overvoltage issue during turn-on transient of the silicon carbide (SiC) junction gate field-effect transistor (JFET) based high voltage super-cascode Power Switch (SCPS) is first identified. The overvoltage issue caused by the JFET slow sequential turn-on is investigated, and the corresponding mitigation method is proposed. Based on this, an optimization method is proposed to improve JFET voltage balancing during off-state as well as eliminating the overvoltage during turn-on transient in the high voltage SiC super-cascode structure. The analysis is verified with experimental results. The overvoltage on the top JFET is eliminated and the total turn-on time is reduced from 518 ns to 82 ns. In the end, the influence of the voltage balancing capacitor tolerance on the voltage distribution is discussed.

R.c. Clarke - One of the best experts on this subject based on the ideXlab platform.

  • 8 kV Normally-off All-SiC Cascode Power Switch Using VJFETs
    Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's, 2007
    Co-Authors: E.j. Stewart, M.j. Mccoy, T.r. Mcnutt, H.c. Hearne, A.p. Walker, S.d. Van Campen, G.m. Bates, S. Leslie, G.c. Desalvo, R.c. Clarke
    Abstract:

    We demonstrate an 8 kV, 3 A cascode Power Switch using SiC VJFETs for both the normally-on and normally-off devices. The normally-on SiC VJFETs have blocking voltages greater than 8 kV at VGS =-50 V pinch-off voltage and on-state currents of more than 4 A at VGS=0 V. The normally-off SiC VJFETs block 70 V (VGS=0 V) and can drive >2 A/device with positive gate voltage (VGS=2.5 V). The VJFETs were combined into a module to create the 8 kV all-SiC cascode Switch that blocks 8 kV normally-off and drives 3 A of on-state current. Preliminary Switching measurements show very fast rise and fall times.

A Marques J Cardoso - One of the best experts on this subject based on the ideXlab platform.

  • Single Power Switch open-circuit fault diagnosis in voltage-fed PWM motor drives by the reference current errors
    8th IEEE Symposium on Diagnostics for Electrical Machines Power Electronics & Drives, 2011
    Co-Authors: Jorge O Estima, A Marques J Cardoso
    Abstract:

    Due to the widespread adoption of variable speed ac drives in many industrial applications, Power converters fault diagnosis is becoming more and more important, particularly for the voltage source inverters used in these systems. Accordingly, this paper presents a new diagnostic method that allows the real-time detection and localization of single Power Switch open-circuit faults in VSI-fed PWM motor drives. The proposed algorithm is quite simple and just requires the measured motor phase currents and their corresponding reference signals, available from the main control system. Several simulation and experimental results using a vector controlled permanent magnet synchronous motor drive are presented, showing the diagnostic method effectiveness, through a relatively fast detection time and its robustness against false alarms.

  • a novel diagnostic method for single Power Switch open circuit faults in voltage fed pwm motor drives
    International Symposium on Power Electronics Electrical Drives Automation and Motion, 2010
    Co-Authors: Jorge O Estima, A Marques J Cardoso
    Abstract:

    Nowadays, variable speed AC drives have become a standard in many industrial applications. Hence, due to the widespread adoption of advanced Power control devices, fault diagnosis of Power converters, in particular the voltage source inverter in variable speed AC drives, is becoming more and more important. Although there are different fault types that may occur in these converters, in this paper, only single Power Switch open-circuit failures are considered in a vector controlled permanent magnet synchronous motor drive. A new real-time algorithm that allows the detection and localization of the faulty device using just the motor phase currents is proposed. Several results under different operating conditions are presented, proving the method effectiveness, low detection time and robustness against false alarms.