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Exploiting FPGA Block Memories for Protected Cryptographic Implementations
'Association for Computing Machinery (ACM)', 2015Co-Authors: Bhasin Shivam, Guilley Sylvain, Danger Jean-luc, He WeiAbstract:Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail Logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.Accepted versio
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Sophisticated security verification on routing repaired balanced cell-based dual-rail Logic against side channel analysis
'Institution of Engineering and Technology (IET)', 2015Co-Authors: He Wei, Bhasin Shivam, Otero Marnotes Andres, Graba Tarik, Eduardo De La ,torre Arnanz, Danger Jean-lucAbstract:Conventional dual-rail Precharge Logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail Logic (BCDL) uses synchronised compound gates with global Precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL
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Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions
E.T.S.I. Industriales (UPM), 2014Co-Authors: He WeiAbstract:Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL Logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de Precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential Logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit Logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the Logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in
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Explointing FPGA block memories for protected cryptographic implementations
'Institute of Electrical and Electronics Engineers (IEEE)', 2013Co-Authors: Bhasin Shivam, Guilley Sylvain, He Wei, Danger Jean-lucAbstract:Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail Logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security
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A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
E.T.S.I. Industriales (UPM), 2011Co-Authors: He Wei, Eduardo De La ,torre Arnanz, Riesgo Alcaide TeresaAbstract:In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this proposal is that the EPE can be effectively prevented by using a synchronized non regular Precharge network, which maintains identical routing between the original and mirror parts, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. Another advantage for our Precharge Absorbed(PA) - DPL method is that its Dual-Core style (independent architecture for true and false parts) could be generated using partial reconfiguration. This helps to get a dynamic security protection with better energy planning. That means system only keeps the true part which fulfills the normal en/decryption task in low security level, and reconfigures the false parts once high security level is required. A relatively limited clock speed is a compromise, since signal propagation is restricted to a portion of the clock period. In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. We experimentally validate our methods in a minimized AES co-processor on Xilinx Virtex-5 board using electromagnetic (EM) attacks
Bhasin Shivam - One of the best experts on this subject based on the ideXlab platform.
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The Other Side of The Coin: Analyzing Software Encoding Schemes Against Fault Injection Attacks
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Breier Jakub, Jap Dirmanto, Bhasin ShivamAbstract:The versatility and cost of embedded systems have made it ubiquitous. Such wide-application exposes an embedded system to a variety of physical threats like side-channel attacks (SCA) and fault attacks (FA). Recently, a couple of software encoding schemes were proposed as a protection against SCA. These protection schemes are based on dual-rail Precharge Logic (DPL), previously shown resistant to both SCA and FA. In this paper, we analyze the previously proposed software encoding schemes against FA. Our results show that software encoding offers only limited resistance to FA. Finally, improvement to software-encoding schemes is improved. With this improvement, software encoding can serve as a common SCA and FA countermeasure with an exploitable fault probability as low as 0.0048.Accepted versio
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Sophisticated security verification on routing repaired balanced cell-based dual-rail Logic against side channel analysis
'Institution of Engineering and Technology (IET)', 2015Co-Authors: He Wei, Bhasin Shivam, Otero Marnotes Andres, Graba Tarik, Eduardo De La ,torre Arnanz, Danger Jean-lucAbstract:Conventional dual-rail Precharge Logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail Logic (BCDL) uses synchronised compound gates with global Precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL
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Exploiting FPGA Block Memories for Protected Cryptographic Implementations
'Association for Computing Machinery (ACM)', 2015Co-Authors: Bhasin Shivam, Guilley Sylvain, Danger Jean-luc, He WeiAbstract:Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail Logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.Accepted versio
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Explointing FPGA block memories for protected cryptographic implementations
'Institute of Electrical and Electronics Engineers (IEEE)', 2013Co-Authors: Bhasin Shivam, Guilley Sylvain, He Wei, Danger Jean-lucAbstract:Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail Logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security
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Contremesures au niveau logique pour sécuriser les architectures de crypto-processeurs dans un FPGA
HAL CCSD, 2011Co-Authors: Bhasin ShivamAbstract:Modern field programmable gate arrays (FPGA) are capable of implementing complex system on chip (SoC) and providing high performance. Therefore, FPGAs are finding wide application. A complex SoC generally contains embedded cryptographic cores to encrypt/decrypt data to ensure security. These cryptographic cores are computationally secure but their physical implementations can be compromised using side channel attacks (SCA) or fault attacks (FA). This thesis focuses on countermeasures for securing cryptographic cores on FPGAs. First, a register-transfer level countermeasure called ''Unrolling'' is proposed. This hiding countermeasure executes multiple rounds of a cryptographic algorithm per clock which allows deeper diffusion of data. Results show excellent resistance against SCA. This is followed by dual-rail Precharge Logic (DPL) based countermeasures, which form a major part of this work. Wave dynamic differential Logic (WDDL), a commonly used DPL countermeasure well suited for FPGAs is studied. Analysis of WDDL (DPL in general) against FA revealed that it is resistant against a majority of faults. Therefore, if flaws in DPL namely early propagation effect (EPE) and technoLogical imbalance are fixed, DPL can evolve as a common countermeasure against SCA and FA. Continuing on this line of research we propose two new countermeasures: DPL without EPE and Balanced-Cell based DPL (BCDL). Finally advanced evaluation tools like stochastic model, mutual information and combined attacks are discussed which are useful when analyzing countermeasures.Les réseaux de portes programmables modernes (FPGA) sont en mesure de mettre enoeuvre un système complexe sur puce (SoC) tout en fournissant des performances élevées. Un SoC Complexe contient généralement des noyaux cryptographiques embarqués permettant de chiffrer/déchiffrer des données afin d'en garantir la sécurité. Ces noyaux cryptographiques sont mathématiquement sûres mais leur mises en oeuvre matérielle peut être compromise par l'utilisation d'attaques par canaux cachés (SCA) ou d'attaques en faute (FA). Tout d'abord, une contremesure ciblant les transferts de registres, que nous appelons "Unrolling" est proposée. Cette contre-mesure exécute plusieurs tours d'un algorithme cryptographique par cycle d'horloge ce qui permet une diffusion plus profonde de données. Les résultats montrent une excellente résistance contre les SCA. Ceci est suivi par une contre-mesure basée sur un "Dual-Rail Precharge Logic" (DPL). La ''Wave Dynamic Differential Logic'' (WDDL) est une contre-mesure DPL bien adaptée pour les FPGAs. L'analyse de la DPL contre les attaques en fautes révéle qu'elle est résistante contre la majorité des fautes. Par conséquent, si des failles comme l'effet de propagation précoce (early propagation effect (EPE)) et le déséquilibre technologique sont fixés, DPL peut évoluer en tant que contre-mesure commune aux SCA et FA. En continuant sur cette ligne de recherche, nous proposons deux nouvelles contremesures: DPL sans EPE et ''Balanced-cell based DPL'' (BCDL). Enfin des outils d'évaluation avancés comme les modèles stochastique, l'information mutuelle et les attaques combinées sont discutées ce qui est très utiles l'analyse des contremesures
Danger Jean-luc - One of the best experts on this subject based on the ideXlab platform.
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Sophisticated security verification on routing repaired balanced cell-based dual-rail Logic against side channel analysis
'Institution of Engineering and Technology (IET)', 2015Co-Authors: He Wei, Bhasin Shivam, Otero Marnotes Andres, Graba Tarik, Eduardo De La ,torre Arnanz, Danger Jean-lucAbstract:Conventional dual-rail Precharge Logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail Logic (BCDL) uses synchronised compound gates with global Precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL
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Exploiting FPGA Block Memories for Protected Cryptographic Implementations
'Association for Computing Machinery (ACM)', 2015Co-Authors: Bhasin Shivam, Guilley Sylvain, Danger Jean-luc, He WeiAbstract:Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail Logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.Accepted versio
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Explointing FPGA block memories for protected cryptographic implementations
'Institute of Electrical and Electronics Engineers (IEEE)', 2013Co-Authors: Bhasin Shivam, Guilley Sylvain, He Wei, Danger Jean-lucAbstract:Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail Logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security
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Low-cost countermeasures against physical attacks on cryptographic algorithms implemented on altera FPGAs
2012Co-Authors: Nassar Maxime, Danger Jean-luc, Guilley SylvainAbstract:Les attaques en fautes (FA) et par canaux cachés (SCA), permettent de récupérer des données sensibles stockées dans des équipements cryptographiques, en exploitant une fuite d'information provenant de leur implémentation matérielle. Le but de cette thèse est donc de formuler un état de l'art des contre-mesures aux SCA adaptées aux FPGA, ainsi que d'implémenter celles qui seront retenues en minimisant les pertes de performance et de complexité. Le cas des algorithmes symétriques tel AES est spécialement étudié, révélant plusieurs faiblesses des contre-mesures habituelles (DPL et masquage) en terme de résistance et de coût. Trois nouvelles contre-mesures sont donc proposées: 1.Des stratégies de placement/routage équilibrés destinées à amélioré la résistance des DPL sur FPGA. 2.Un nouveau type de DPL appelée BCDL (Balanced Cell-based Dual-rail Logic) dont le but est de supprimer la plupart des vulnérabilités liées aux DPLs. BCDL est également résilient à la majeure partie des FA et optimisé pour les FPGA, ce qui induit des complexité et performance compétitives. 3. RSM (Rotating S-Box Masking), une nouvelle technique de masquage pour AES qui montre un haut niveau de performances et résistance pour une complexité réduite. Finalement, plusieurs nouvelles SCA sont présentées et évaluées. RC (Rank Corrector) est un algorithme permettant d'améliorer les autres SCA. La FPCA introduit un nouveau distingueur basée sur la PCA. Puis plusieurs combinaisons (distingueur et mesures) sont proposées et résultent en une diminution du nombre de trace nécessaire à l'attaque.Side-Channel Analysis (SCA) and Fault Attacks (FA) are techniques to recover sensitive information in cryptographic systems by exploiting unintentional physical leakage, such as the power consumption. This thesis has two main goals: to draw a review of the state of the art of FPGA-compatible countermeasures against SCA and implement t the selected ones with the minimum area and performances overhead. Symmetrical algorithms, specially AES, are studied and several vulnerabilities of usual protections, namely Dual-rail with Precharge Logic (DPL) and masking are analysed, as well as the issue of performance and area overheads. In this context, three new countermeasures are considered: 1. Balance placement and routing (PAR) strategies aiming at enhancing existing DPLs robustness when implemented in modern FPGAs. 2. A new type of DPL called Balanced Cell-based Dual-railLogic (BCDL), to thwart most of the known DPL weaknesses. BCDL also possess a fault resilience mechanism and provides implementation optimisations on FPGA, achieving competitive performances and area overhead. 3. The Rotating S-Box Masking (RSM), a new masking technique for the AES that shows high leveles of robustness and performances while bringing a significant reduction of the area overhead. Finally, several new SCAs are presented and evaluated. Firstly the Rank Corrector a SCA enhancement algorithm. Secondly, The FPCA, introduces a novel SCA distinguisher based on the PCA. Then, combinations of either acquisition methods or SCA distinguishers are discussed and show significant decrease in the number of measurements required to perform a successful attack.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF
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Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.
HAL CCSD, 2009Co-Authors: Sauvage Laurent, Guilley Sylvain, Danger Jean-luc, Mathieu Yves, Nassar MaximeAbstract:International audienceIn this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method is that it uses intrinsic characteristics of the countermeasure: classical methods fail when the countermeasure is perfect, whereas our method still works and enables us to perform advanced attacks. We have experimentally validated the proposed method by attacking a DES cryptoprocessor embedded in a Field Programmable Gates Array (FPGA), and protected by the Wave Dynamic Differential Logic (WDDL) countermeasure. This successful attack, unambiguous as the full key is retrieved, is the first to be reported
Guilley Sylvain - One of the best experts on this subject based on the ideXlab platform.
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Exploiting FPGA Block Memories for Protected Cryptographic Implementations
'Association for Computing Machinery (ACM)', 2015Co-Authors: Bhasin Shivam, Guilley Sylvain, Danger Jean-luc, He WeiAbstract:Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail Logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.Accepted versio
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Explointing FPGA block memories for protected cryptographic implementations
'Institute of Electrical and Electronics Engineers (IEEE)', 2013Co-Authors: Bhasin Shivam, Guilley Sylvain, He Wei, Danger Jean-lucAbstract:Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail Logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security
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Protection des Accélérateurs Matériels de Cryptographie Symétrique
HAL CCSD, 2012Co-Authors: Guilley SylvainAbstract:385 pagesLes contremesures de masquage et de dissimulation permettent de rendre plus compliquées les attaques sur les implémentations de chiffrement symétrique. Elles sont aussi toutes deux aisément implémentables (et ce de façon automatisable) dans des flots EDA (Electronic Design Automation) pour ASIC (Application Specific Integrated Circuit) ou FPGA (Field Programmable Gates Array), avec certes différents niveaux d'expertise requis selon la contremesure concernée. Le masquage assure une protection "dynamique" s'appuyant sur un mélange d'aléa en cours de calcul. Nous montrons comment optimiser l'usage de cet aléa grâce à un codage qui permet de compresser les fuites d'information (leakage squeezing). Les limites du masquage s'étudient grâce à des outils de statistique, en analysant des distributions de probabilités. L'outil maître pour évaluer les imperfections des logiques DPL (Dual-rail with Precharge Logic style) est l'analyse stochastique, qui tente de modéliser des fuites "statiques" combinant plusieurs bits. L'inconvénient du masquage est que les attaques sont structurelles à l'utilisation d'aléa : si une attaque réussit sur une partie de la clé (e.g. un octet), alors a priori tous les autres octets sont de façon consistante vulnérables à la même attaque. La situation est différente avec les DPL : en cas de problème d'implémentation, seuls les octets de clés impliqués dans les parties déséquilibrées sont compromis, et non toute la clé. Une façon encore moins coûteuse de protéger les implémentations cryptographiques contre les attaques physiques est la résilience. C'est un usage astucieux de primitives a priori non protégées qui permet d'assurer la protection des secrets. L'avantage des approches résilientes est leur simplicité de mise en oeuvre et (idéalement), leur prouvabilité. Le principal inconvénient est que les contraintes d'usage ne sont souvent pas compatibles avec les standards actuels. Ainsi, nous pensons que davantage de recherche dans ce domaine pourrait globalement être profitable à l'industrie de la sécurité de systèmes embarqués
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Low-cost countermeasures against physical attacks on cryptographic algorithms implemented on altera FPGAs
2012Co-Authors: Nassar Maxime, Danger Jean-luc, Guilley SylvainAbstract:Les attaques en fautes (FA) et par canaux cachés (SCA), permettent de récupérer des données sensibles stockées dans des équipements cryptographiques, en exploitant une fuite d'information provenant de leur implémentation matérielle. Le but de cette thèse est donc de formuler un état de l'art des contre-mesures aux SCA adaptées aux FPGA, ainsi que d'implémenter celles qui seront retenues en minimisant les pertes de performance et de complexité. Le cas des algorithmes symétriques tel AES est spécialement étudié, révélant plusieurs faiblesses des contre-mesures habituelles (DPL et masquage) en terme de résistance et de coût. Trois nouvelles contre-mesures sont donc proposées: 1.Des stratégies de placement/routage équilibrés destinées à amélioré la résistance des DPL sur FPGA. 2.Un nouveau type de DPL appelée BCDL (Balanced Cell-based Dual-rail Logic) dont le but est de supprimer la plupart des vulnérabilités liées aux DPLs. BCDL est également résilient à la majeure partie des FA et optimisé pour les FPGA, ce qui induit des complexité et performance compétitives. 3. RSM (Rotating S-Box Masking), une nouvelle technique de masquage pour AES qui montre un haut niveau de performances et résistance pour une complexité réduite. Finalement, plusieurs nouvelles SCA sont présentées et évaluées. RC (Rank Corrector) est un algorithme permettant d'améliorer les autres SCA. La FPCA introduit un nouveau distingueur basée sur la PCA. Puis plusieurs combinaisons (distingueur et mesures) sont proposées et résultent en une diminution du nombre de trace nécessaire à l'attaque.Side-Channel Analysis (SCA) and Fault Attacks (FA) are techniques to recover sensitive information in cryptographic systems by exploiting unintentional physical leakage, such as the power consumption. This thesis has two main goals: to draw a review of the state of the art of FPGA-compatible countermeasures against SCA and implement t the selected ones with the minimum area and performances overhead. Symmetrical algorithms, specially AES, are studied and several vulnerabilities of usual protections, namely Dual-rail with Precharge Logic (DPL) and masking are analysed, as well as the issue of performance and area overheads. In this context, three new countermeasures are considered: 1. Balance placement and routing (PAR) strategies aiming at enhancing existing DPLs robustness when implemented in modern FPGAs. 2. A new type of DPL called Balanced Cell-based Dual-railLogic (BCDL), to thwart most of the known DPL weaknesses. BCDL also possess a fault resilience mechanism and provides implementation optimisations on FPGA, achieving competitive performances and area overhead. 3. The Rotating S-Box Masking (RSM), a new masking technique for the AES that shows high leveles of robustness and performances while bringing a significant reduction of the area overhead. Finally, several new SCAs are presented and evaluated. Firstly the Rank Corrector a SCA enhancement algorithm. Secondly, The FPCA, introduces a novel SCA distinguisher based on the PCA. Then, combinations of either acquisition methods or SCA distinguishers are discussed and show significant decrease in the number of measurements required to perform a successful attack.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF
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Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.
HAL CCSD, 2009Co-Authors: Sauvage Laurent, Guilley Sylvain, Danger Jean-luc, Mathieu Yves, Nassar MaximeAbstract:International audienceIn this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method is that it uses intrinsic characteristics of the countermeasure: classical methods fail when the countermeasure is perfect, whereas our method still works and enables us to perform advanced attacks. We have experimentally validated the proposed method by attacking a DES cryptoprocessor embedded in a Field Programmable Gates Array (FPGA), and protected by the Wave Dynamic Differential Logic (WDDL) countermeasure. This successful attack, unambiguous as the full key is retrieved, is the first to be reported
Nassar Maxime - One of the best experts on this subject based on the ideXlab platform.
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Low-cost countermeasures against physical attacks on cryptographic algorithms implemented on altera FPGAs
2012Co-Authors: Nassar MaximeAbstract:Les attaques en fautes (FA) et par canaux cachés (SCA), permettent de récupérer des données sensibles stockées dans des équipements cryptographiques, en exploitant une fuite d'information provenant de leur implémentation matérielle. Le but de cette thèse est donc de formuler un état de l'art des contre-mesures aux SCA adaptées aux FPGA, ainsi que d'implémenter celles qui seront retenues en minimisant les pertes de performance et de complexité. Le cas des algorithmes symétriques tel AES est spécialement étudié, révélant plusieurs faiblesses des contre-mesures habituelles (DPL et masquage) en terme de résistance et de coût. Trois nouvelles contre-mesures sont donc proposées: 1.Des stratégies de placement/routage équilibrés destinées à amélioré la résistance des DPL sur FPGA. 2.Un nouveau type de DPL appelée BCDL (Balanced Cell-based Dual-rail Logic) dont le but est de supprimer la plupart des vulnérabilités liées aux DPLs. BCDL est également résilient à la majeure partie des FA et optimisé pour les FPGA, ce qui induit des complexité et performance compétitives. 3. RSM (Rotating S-Box Masking), une nouvelle technique de masquage pour AES qui montre un haut niveau de performances et résistance pour une complexité réduite. Finalement, plusieurs nouvelles SCA sont présentées et évaluées. RC (Rank Corrector) est un algorithme permettant d'améliorer les autres SCA. La FPCA introduit un nouveau distingueur basée sur la PCA. Puis plusieurs combinaisons (distingueur et mesures) sont proposées et résultent en une diminution du nombre de trace nécessaire à l'attaque.Side-Channel Analysis (SCA) and Fault Attacks (FA) are techniques to recover sensitive information in cryptographic systems by exploiting unintentional physical leakage, such as the power consumption. This thesis has two main goals: to draw a review of the state of the art of FPGA-compatible countermeasures against SCA and implement t the selected ones with the minimum area and performances overhead. Symmetrical algorithms, specially AES, are studied and several vulnerabilities of usual protections, namely Dual-rail with Precharge Logic (DPL) and masking are analysed, as well as the issue of performance and area overheads. In this context, three new countermeasures are considered: 1. Balance placement and routing (PAR) strategies aiming at enhancing existing DPLs robustness when implemented in modern FPGAs. 2. A new type of DPL called Balanced Cell-based Dual-railLogic (BCDL), to thwart most of the known DPL weaknesses. BCDL also possess a fault resilience mechanism and provides implementation optimisations on FPGA, achieving competitive performances and area overhead. 3. The Rotating S-Box Masking (RSM), a new masking technique for the AES that shows high leveles of robustness and performances while bringing a significant reduction of the area overhead. Finally, several new SCAs are presented and evaluated. Firstly the “Rank Corrector” a SCA enhancement algorithm. Secondly, The FPCA, introduces a novel SCA distinguisher based on the PCA. Then, combinations of either acquisition methods or SCA distinguishers are discussed and show significant decrease in the number of measurements required to perform a successful attack
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Low-cost countermeasures against physical attacks on cryptographic algorithms implemented on altera FPGAs
2012Co-Authors: Nassar Maxime, Danger Jean-luc, Guilley SylvainAbstract:Les attaques en fautes (FA) et par canaux cachés (SCA), permettent de récupérer des données sensibles stockées dans des équipements cryptographiques, en exploitant une fuite d'information provenant de leur implémentation matérielle. Le but de cette thèse est donc de formuler un état de l'art des contre-mesures aux SCA adaptées aux FPGA, ainsi que d'implémenter celles qui seront retenues en minimisant les pertes de performance et de complexité. Le cas des algorithmes symétriques tel AES est spécialement étudié, révélant plusieurs faiblesses des contre-mesures habituelles (DPL et masquage) en terme de résistance et de coût. Trois nouvelles contre-mesures sont donc proposées: 1.Des stratégies de placement/routage équilibrés destinées à amélioré la résistance des DPL sur FPGA. 2.Un nouveau type de DPL appelée BCDL (Balanced Cell-based Dual-rail Logic) dont le but est de supprimer la plupart des vulnérabilités liées aux DPLs. BCDL est également résilient à la majeure partie des FA et optimisé pour les FPGA, ce qui induit des complexité et performance compétitives. 3. RSM (Rotating S-Box Masking), une nouvelle technique de masquage pour AES qui montre un haut niveau de performances et résistance pour une complexité réduite. Finalement, plusieurs nouvelles SCA sont présentées et évaluées. RC (Rank Corrector) est un algorithme permettant d'améliorer les autres SCA. La FPCA introduit un nouveau distingueur basée sur la PCA. Puis plusieurs combinaisons (distingueur et mesures) sont proposées et résultent en une diminution du nombre de trace nécessaire à l'attaque.Side-Channel Analysis (SCA) and Fault Attacks (FA) are techniques to recover sensitive information in cryptographic systems by exploiting unintentional physical leakage, such as the power consumption. This thesis has two main goals: to draw a review of the state of the art of FPGA-compatible countermeasures against SCA and implement t the selected ones with the minimum area and performances overhead. Symmetrical algorithms, specially AES, are studied and several vulnerabilities of usual protections, namely Dual-rail with Precharge Logic (DPL) and masking are analysed, as well as the issue of performance and area overheads. In this context, three new countermeasures are considered: 1. Balance placement and routing (PAR) strategies aiming at enhancing existing DPLs robustness when implemented in modern FPGAs. 2. A new type of DPL called Balanced Cell-based Dual-railLogic (BCDL), to thwart most of the known DPL weaknesses. BCDL also possess a fault resilience mechanism and provides implementation optimisations on FPGA, achieving competitive performances and area overhead. 3. The Rotating S-Box Masking (RSM), a new masking technique for the AES that shows high leveles of robustness and performances while bringing a significant reduction of the area overhead. Finally, several new SCAs are presented and evaluated. Firstly the Rank Corrector a SCA enhancement algorithm. Secondly, The FPCA, introduces a novel SCA distinguisher based on the PCA. Then, combinations of either acquisition methods or SCA distinguishers are discussed and show significant decrease in the number of measurements required to perform a successful attack.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF
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Contre-mesures à bas coût contre les attaques physiques sur algorithmes cryptographiques implémentés sur FPGA Altera
HAL CCSD, 2012Co-Authors: Nassar MaximeAbstract:Side-Channel Analysis (SCA) and Fault Attacks (FA) are techniques to recover sensitive information in cryptographic systems by exploiting unintentional physical leakage, such as the power consumption. This thesis has two main goals: to draw a review of the state of the art of FPGA-compatible countermeasures against SCA and implement t the selected ones with the minimum area and performances overhead. Symmetrical algorithms, specially AES, are studied and several vulnerabilities of usual protections, namely Dual-rail with Precharge Logic (DPL) and masking are analysed, as well as the issue of performance and area overheads. In this context, three new countermeasures are considered: 1. Balance placement and routing (PAR) strategies aiming at enhancing existing DPLs robustness when implemented in modern FPGAs. 2. A new type of DPL called Balanced Cell-based Dual-railLogic (BCDL), to thwart most of the known DPL weaknesses. BCDL also possess a fault resilience mechanism and provides implementation optimisations on FPGA, achieving competitive performances and area overhead. 3. The Rotating S-Box Masking (RSM), a new masking technique for the AES that shows high leveles of robustness and performances while bringing a significant reduction of the area overhead. Finally, several new SCAs are presented and evaluated. Firstly the "Rank Corrector" a SCA enhancement algorithm. Secondly, The FPCA, introduces a novel SCA distinguisher based on the PCA. Then, combinations of either acquisition methods or SCA distinguishers are discussed and show significant decrease in the number of measurements required to perform a successful attack.Les attaques en fautes (FA) et par canaux cachés (SCA), permettent de récupérer des données sensibles stockées dans des équipements cryptographiques, en exploitant une fuite d'information provenant de leur implémentation matérielle. Le but de cette thèse est donc de formuler un état de l'art des contre-mesures aux SCA adaptées aux FPGA, ainsi que d'implémenter celles qui seront retenues en minimisant les pertes de performance et de complexité. Le cas des algorithmes symétriques tel AES est spécialement étudié, révélant plusieurs faiblesses des contre-mesures habituelles (DPL et masquage) en terme de résistance et de coût. Trois nouvelles contre-mesures sont donc proposées: 1.Des stratégies de placement/routage équilibrés destinées à amélioré la résistance des DPL sur FPGA. 2.Un nouveau type de DPL appelée BCDL (Balanced Cell-based Dual-rail Logic) dont le but est de supprimer la plupart des vulnérabilités liées aux DPLs. BCDL est également résilient à la majeure partie des FA et optimisé pour les FPGA, ce qui induit des complexité et performance compétitives. 3. RSM (Rotating S-Box Masking), une nouvelle technique de masquage pour AES qui montre un haut niveau de performances et résistance pour une complexité réduite. Finalement, plusieurs nouvelles SCA sont présentées et évaluées. RC (Rank Corrector) est un algorithme permettant d'améliorer les autres SCA. La FPCA introduit un nouveau distingueur basée sur la PCA. Puis plusieurs combinaisons (distingueur et mesures) sont proposées et résultent en une diminution du nombre de trace nécessaire à l'attaque
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Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.
HAL CCSD, 2009Co-Authors: Sauvage Laurent, Guilley Sylvain, Danger Jean-luc, Mathieu Yves, Nassar MaximeAbstract:International audienceIn this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method is that it uses intrinsic characteristics of the countermeasure: classical methods fail when the countermeasure is perfect, whereas our method still works and enables us to perform advanced attacks. We have experimentally validated the proposed method by attacking a DES cryptoprocessor embedded in a Field Programmable Gates Array (FPGA), and protected by the Wave Dynamic Differential Logic (WDDL) countermeasure. This successful attack, unambiguous as the full key is retrieved, is the first to be reported