The Experts below are selected from a list of 14475 Experts worldwide ranked by ideXlab platform
William H Owen - One of the best experts on this subject based on the ideXlab platform.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high précision 500-nA CMOS floating-gate analog Voltage reference
2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high Precision 500-nA CMOS floating-gate analog Voltage reference
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC)
Bhupendra K Ahuja - One of the best experts on this subject based on the ideXlab platform.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high précision 500-nA CMOS floating-gate analog Voltage reference
2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high Precision 500-nA CMOS floating-gate analog Voltage reference
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC)
Carlos Laber - One of the best experts on this subject based on the ideXlab platform.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high précision 500-nA CMOS floating-gate analog Voltage reference
2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high Precision 500-nA CMOS floating-gate analog Voltage reference
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC)
Laleh Najafizadeh - One of the best experts on this subject based on the ideXlab platform.
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single event transient and total dose response of Precision Voltage reference circuits designed in a 90 nm sige bicmos technology
IEEE Transactions on Nuclear Science, 2014Co-Authors: Adilson S Cardoso, Partha S Chakraborty, Nedeljko Karaulac, David M Fleischhauer, Nelson E Lourenco, Zachary E Fleetwood, Anup P Omprakash, Troy D England, Seungwoo Jung, Laleh NajafizadehAbstract:This paper presents an investigation of the impact of single-event transients (SETs) and total ionization dose (TID) on Precision Voltage reference circuits designed in a fourth-generation, 90-nm SiGe BiCMOS technology. A first-order uncompensated bandgap reference (BGR) circuit is used to benchmark the SET and TID responses of these Voltage reference circuits (VRCs). Based on the first-order BGR radiation response, new circuit-level radiation-hardening-by-design (RHBD) techniques are proposed. An RHBD technique using inverse-mode (IM) transistors is demonstrated in a BGR circuit. In addition, a PIN diode VRC is presented as a potential SET and TID tolerant, circuit-level RHBD alternative.
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a comparison of the effects of x ray and proton irradiation on the performance of sige Precision Voltage references
IEEE Transactions on Nuclear Science, 2007Co-Authors: Laleh Najafizadeh, John D Cressler, M Bellini, P W Marshall, A K Sutton, R M Diestelhorst, Bongim Jun, C J MarshallAbstract:A comprehensive investigation of the performance dependencies of irradiated SiGe Precision Voltage reference circuits on (1) total ionizing dose (TID), (2) circuit topology, and (3) radiation source is presented. Two different bandgap Voltage references were designed using a first-generation (50-GHz) SiGe BiCMOS technology platform, and subsequently exposed to X-rays at doses of 1080 krad(SiO2) and 5400 krad(SiO2). The degradation in circuit performance following X-ray irradiation depends on both the TID level and the chosen circuit topology. Measurement results show that large TID levels can significantly shift the magnitude of the output Voltage. Explanations for the observed shifts are provided by utilizing detailed analyses of the two circuit topologies and considering device-to-circuit interactions. The primary factor responsible for the difference in the circuit response before and after irradiation can be attributed to the excess base leakage current in the SiGe HBT. To investigate the impact of radiation source, the circuit topology showing the worst-case degradation from the X-ray experiment was independently exposed to 63-MeV protons at the same effective TID level. A clear source dependence in the circuit response was observed, and possible origins of this behavior are identified.
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proton tolerance of sige Precision Voltage references for extreme temperature range electronics
IEEE Transactions on Nuclear Science, 2006Co-Authors: Laleh Najafizadeh, John D Cressler, M Bellini, A P G Prakash, G Espinel, P W Marshall, C J MarshallAbstract:A comprehensive investigation of the effects of proton irradiation on the performance of SiGe BiCMOS Precision Voltage references intended for extreme environment operational conditions is presented. The Voltage reference circuits were designed in two distinct SiGe BiCMOS technology platforms (first generation (50 GHz) and third generation (200 GHz)) in order to investigate the effect of technology scaling. The circuits were irradiated at both room temperature and at 77 K. Measurement results from the experiments indicate that the proton-induced changes in the SiGe bandgap references are minor, even down to cryogenic temperatures, clearly good news for the potential application of SiGe mixed-signal circuits in emerging extreme environments
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sige bicmos Precision Voltage references for extreme temperature range electronics
Bipolar BiCMOS Circuits and Technology Meeting, 2006Co-Authors: Laleh Najafizadeh, Chendong Zhu, R Krithivasan, John D Cressler, Yan Cui, Guofu Niu, Suheng Chen, Chandradevi Ulaganathan, Benjamin J Blalock, Alvin J JosephAbstract:We present the first investigation of the optimal implementation of SiGe BiCMOS Precision Voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on Precision Voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications
Hoa Vu - One of the best experts on this subject based on the ideXlab platform.
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a very high Precision 500 na cmos floating gate analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high Precision 500 na cmos floating gate analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a Precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.