The Experts below are selected from a list of 36 Experts worldwide ranked by ideXlab platform

Wen-mei W. Hwu - One of the best experts on this subject based on the ideXlab platform.

  • Execution Flow Code Layout Action
    2009
    Co-Authors: Matthew C. Merten, Wen-mei W. Hwu
    Abstract:

    As VLIW/EPIC processors are increasingly used in realtime, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernelonly modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the Predicate Register file, allowing for a less rigorous predication implementation. Finally, hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation. 1

  • Enhancing Loop Buffering of Media and Telecommunications Applications Using Low-Overhead Predication
    2001
    Co-Authors: John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Abstract:

    Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, staticallyscheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem---full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into Predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a Predicate Register-based approach

  • Modulo Schedule Buffers
    2001
    Co-Authors: Matthew C. Merten, Wen-mei W. Hwu
    Abstract:

    As VLIW/EPIC processors are increasingly used in realtime, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernelonly modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the Predicate Register file, allowing for a less rigorous predication implementation. Finally, hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation. 1

  • MICRO - Enhancing loop buffering of media and telecommunications applications using low-overhead predication
    Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1
    Co-Authors: John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Abstract:

    Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, statically-scheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem---full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into Predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a Predicate Register-based approach.

  • MICRO - Modulo schedule buffers
    Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1
    Co-Authors: Matthew C. Merten, Wen-mei W. Hwu
    Abstract:

    As VLIW/EPIC processors are increasingly used in real-time, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernel-only modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the Predicate Register file, allowing for a less rigorous predication implementation. Finally; hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation.

John W. Sias - One of the best experts on this subject based on the ideXlab platform.

  • Enhancing Loop Buffering of Media and Telecommunications Applications Using Low-Overhead Predication
    2001
    Co-Authors: John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Abstract:

    Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, staticallyscheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem---full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into Predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a Predicate Register-based approach

  • MICRO - Enhancing loop buffering of media and telecommunications applications using low-overhead predication
    Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1
    Co-Authors: John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Abstract:

    Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, statically-scheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem---full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into Predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a Predicate Register-based approach.

Felicity Colman - One of the best experts on this subject based on the ideXlab platform.

  • Digital Feminicity: Predication and Measurement, Materialist Informatics and Images
    Artnodes, 2014
    Co-Authors: Felicity Colman
    Abstract:

    “Feminicity” is the term for a Predicate Register that enables feminist work be accounted for as relational “active-points” (as an alternative formulation to standpoints) that collectively can be seen through what they have achieved. But going further, it marks where those active-points contribute to the dynamic field of feminist epistemologies and where change occurs. This article contributes to my larger project’s discussion of this concept. Broadly, feminicity argues that the active-points of feminist practices (practical and conceptual) need to be understood within their situated fields as materialist informatics. In the digital era, examples of the affects of digital feminicity are as identified in works such as those by Wajcman (1991; 2004); Haraway (1993; Nakamura, 2003), Hayles (1993; 2012), VNSMatrix (1991), Adam (1998), Plant (1998). Collectively, such authors and artists opened a creative, and sometimes radical discourse of the digital field as multidirectional, multidimensional, multitemporal platform of “gender actions”. Taken as a Predicated field (using Gottlob Frege’s (1964) sense of the term “Predicate”), this work contributes to the feminist materialist reappraisal of feminist epistemology (cf. Alaimo and Hekman, 2008; Van Der Tuin, 2014), and larger radical feminist deconstructive projects (Malabou, 2011; Fraser, 2013). Thus conceived, the genealogy of digital feminicity problematizes the monopolitical terms of feminism in its collation of actions, enabling a re-situation of feminist practices as positive material interventions and expressions of the ontological constitution of the political sphere. Feminicity does not propose a chronological account of the active-points, but processually and systemically addresses the terms of generational epistemological political change (Olkowski, 1999; Van Der Tuin 2014). This article describes the ways in which a materialist constructed Register — “feminicity”— can be used to think about encounters between the domains of gender, politics and technology, as manifested by materialist informatics. For reasons of brevity, this article focuses on just two aspects of feminicity: the terms of predication of the female as gendered, and the issue of the image, as digital informatics, comprised of activity-points of feminist practice. Consequently, these are measurable and offer practical resources for the general problem of gendering politics that operate in governance, resource distribution and a non-equal opportunity social/cultural power structure, under which minorities are disadvantaged. Feminist practice here refers to forms produced through feminist activities, i.e., forms generated through relations with the matter of life through specific modalities of needs-based practices (inclusive of intuition, compulsion, capitalist-driven practices of utility, theory and art).

  • Feminicitat digital: predicacio i mesurament, informatica i imatges = Digital feminicity : predication and measurement, informatics and images
    2014
    Co-Authors: Felicity Colman
    Abstract:

    “Feminicity” is the term for a Predicate Register that enables feminist work be accounted for as relational “active-points” (as an alternative formulation to standpoints) that collectively can be seen through what they have achieved. But going further, it marks where those active-points contribute to the dynamic field of feminist epistemologies and where change occurs. This article contributes to my larger project’s discussion of this concept. Broadly, feminicity argues that the active-points of feminist practices (practical and conceptual) need to be understood within their situated fields as materialist informatics. In the digital era, examples of the affects of digital feminicity are as identified in works such as those by Wajcman (1991; 2004); Haraway (1993; Nakamura, 2003), Hayles (1993; 2012), VNSMatrix (1991), Adam (1998), Plant (1998). Collectively, such authors and artists opened a creative, and sometimes radical discourse of the digital field as multidirectional, multidimensional, multitemporal platform of “gender actions”. Taken as a Predicated field (using Gottlob Frege’s (1964) sense of the term “Predicate”), this work contributes to the feminist materialist reappraisal of feminist epistemology (cf. Alaimo and Hekman, 2008; Van Der Tuin, 2014), and larger radical feminist deconstructive projects (Malabou, 2011; Fraser, 2013). Thus conceived, the genealogy of digital feminicity problematizes the monopolitical terms of feminism in its collation of actions, enabling a re-situation of feminist practices as positive material interventions and expressions of the ontological constitution of the political sphere. Feminicity does not propose a chronological account of the active-points, but processually and systemically addresses the terms of generational epistemological political change (Olkowski, 1999; Van Der Tuin 2014). This article describes the ways in which a materialist constructed Register — “feminicity”— can be used to think about encounters between the domains of gender, politics and technology, as manifested by materialist informatics. For reasons of brevity, this article focuses on just two aspects of feminicity: the terms of predication of the female as gendered, and the issue of the image, as digital informatics, comprised of activity-points of feminist practice. Consequently, these are measurable and offer practical resources for the general problem of gendering politics that operate in governance, resource distribution and a non-equal opportunity social/cultural power structure, under which minorities are disadvantaged. Feminist practice here refers to forms produced through feminist activities, i.e., forms generated through relations with the matter of life through specific modalities of needs-based practices (inclusive of intuition, compulsion, capitalist-driven practices of utility, theory and art).

Hillery C. Hunter - One of the best experts on this subject based on the ideXlab platform.

  • Enhancing Loop Buffering of Media and Telecommunications Applications Using Low-Overhead Predication
    2001
    Co-Authors: John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Abstract:

    Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, staticallyscheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem---full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into Predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a Predicate Register-based approach

  • MICRO - Enhancing loop buffering of media and telecommunications applications using low-overhead predication
    Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1
    Co-Authors: John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Abstract:

    Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, statically-scheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem---full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into Predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a Predicate Register-based approach.

Matthew C. Merten - One of the best experts on this subject based on the ideXlab platform.

  • Execution Flow Code Layout Action
    2009
    Co-Authors: Matthew C. Merten, Wen-mei W. Hwu
    Abstract:

    As VLIW/EPIC processors are increasingly used in realtime, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernelonly modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the Predicate Register file, allowing for a less rigorous predication implementation. Finally, hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation. 1

  • Modulo Schedule Buffers
    2001
    Co-Authors: Matthew C. Merten, Wen-mei W. Hwu
    Abstract:

    As VLIW/EPIC processors are increasingly used in realtime, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernelonly modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the Predicate Register file, allowing for a less rigorous predication implementation. Finally, hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation. 1

  • MICRO - Modulo schedule buffers
    Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1
    Co-Authors: Matthew C. Merten, Wen-mei W. Hwu
    Abstract:

    As VLIW/EPIC processors are increasingly used in real-time, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernel-only modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the Predicate Register file, allowing for a less rigorous predication implementation. Finally; hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation.