The Experts below are selected from a list of 57 Experts worldwide ranked by ideXlab platform
Andy D Pimentel - One of the best experts on this subject based on the ideXlab platform.
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a combined hardware software solution for stream Prefetching in multimedia applications
Proceedings of SPIE, 1998Co-Authors: P Struik, P Van Der Wolf, Andy D PimentelAbstract:Prefetch techniques may, in general, be applied to reduce the miss rate of a processor's data cache and thereby improve the overall performance of the processor. More in particular, stream Prefetch techniques can be applied to Prefetch data streams that are often encountered in multimedia applications. Stream Prefetch techniques exploit the fact that data from such streams are often accessed in a regular fashion. Implementing a stream Prefetch technique involves two issues, viz. stream combined hardware/software stream Prefetch technique. A special stream-Prefetch Instruction is introduced to alert the hardware that load Instructions access a data stream. Subsequently, Prefetching is handled by the hardware automatically in such a way that the rate at which the data is Prefetched is synchronized with the rate at which the Prefetched data is processed by the application. These kinds of stream Prefetch techniques have been proposed earlier but use Instruction addresses for synchronization. The technique that is introduced in this paper uses a different synchronization mechanism that does not suffer from drawbacks of Instruction address synchronization.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
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A combined hardware/software solution for stream Prefetching in multimedia applications
Multimedia Hardware Architectures 1998, 1998Co-Authors: P Struik, P. Van Der Wolf, Andy D PimentelAbstract:Prefetch techniques may, in general, be applied to reduce the miss rate of a processor's data cache and thereby improve the overall performance of the processor. More in particular, stream Prefetch techniques can be applied to Prefetch data streams that are often encountered in multimedia applications. Stream Prefetch techniques exploit the fact that data from such streams are often accessed in a regular fashion. Implementing a stream Prefetch technique involves two issues, viz. stream combined hardware/software stream Prefetch technique. A special stream-Prefetch Instruction is introduced to alert the hardware that load Instructions access a data stream. Subsequently, Prefetching is handled by the hardware automatically in such a way that the rate at which the data is Prefetched is synchronized with the rate at which the Prefetched data is processed by the application. These kinds of stream Prefetch techniques have been proposed earlier but use Instruction addresses for synchronization. The technique that is introduced in this paper uses a different synchronization mechanism that does not suffer from drawbacks of Instruction address synchronization.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Philippe Clauss - One of the best experts on this subject based on the ideXlab platform.
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Performance driven data cache Prefetching in a dynamic software optimization system
2007Co-Authors: Jean Christophe Beyler, Philippe ClaussAbstract:Software or hardware data cache Prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued Prefetches have to be monitored in order to maximize their positive impact while minimizing their negative impact on performance. In previous proposed dynamic frameworks, the monitoring scheme is either achieved using processor performance counters or using specific hardware. In this work, we propose a Prefetching strategy which does not use any specific hardware component or processor performance counter. Our dynamic framework wants to be portable on any modern processor architecture providing at least a Prefetch Instruction. Opportunity and effectiveness of Prefetching loads is simply guided by the time spent to effectively obtain the data. Every load of a program is monitored periodically and can be either associated to a dynamically inserted Prefetch Instruction or not. It can be associated to a Prefetch Instruction at some disjoint periods of the whole program run as soon as it is efficient. Our framework has been implemented for Itanium-2 machines. It involves several dynamic instrumentations of the binary code whose overhead is limited to only 4% on average. On a large set of benchmarks, our system is able to speed up some programs by 2%--143%.
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ICS - Performance driven data cache Prefetching in a dynamic software optimization system
Proceedings of the 21st annual international conference on Supercomputing - ICS '07, 2007Co-Authors: Jean Christophe Beyler, Philippe ClaussAbstract:Software or hardware data cache Prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued Prefetches have to be monitored in order to maximize their positive impact while minimizing their negative impact on performance. In previous proposed dynamic frameworks, the monitoring scheme is either achieved using processor performance counters or using specific hardware. In this work, we propose a Prefetching strategy which does not use any specific hardware component or processor performance counter. Our dynamic framework wants to be portable on any modern processor architecture providing at least a Prefetch Instruction. Opportunity and effectiveness of Prefetching loads is simply guided by the time spent to effectively obtain the data. Every load of a program is monitored periodically and can be either associated to a dynamically inserted Prefetch Instruction or not. It can be associated to a Prefetch Instruction at some disjoint periods of the whole program run as soon as it is efficient. Our framework has been implemented for Itanium-2 machines. It involves several dynamic instrumentations of the binary code whose overhead is limited to only 4% on average. On a large set of benchmarks, our system is able to speed up some programs by 2%--143%.
P Struik - One of the best experts on this subject based on the ideXlab platform.
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a combined hardware software solution for stream Prefetching in multimedia applications
Proceedings of SPIE, 1998Co-Authors: P Struik, P Van Der Wolf, Andy D PimentelAbstract:Prefetch techniques may, in general, be applied to reduce the miss rate of a processor's data cache and thereby improve the overall performance of the processor. More in particular, stream Prefetch techniques can be applied to Prefetch data streams that are often encountered in multimedia applications. Stream Prefetch techniques exploit the fact that data from such streams are often accessed in a regular fashion. Implementing a stream Prefetch technique involves two issues, viz. stream combined hardware/software stream Prefetch technique. A special stream-Prefetch Instruction is introduced to alert the hardware that load Instructions access a data stream. Subsequently, Prefetching is handled by the hardware automatically in such a way that the rate at which the data is Prefetched is synchronized with the rate at which the Prefetched data is processed by the application. These kinds of stream Prefetch techniques have been proposed earlier but use Instruction addresses for synchronization. The technique that is introduced in this paper uses a different synchronization mechanism that does not suffer from drawbacks of Instruction address synchronization.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
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A combined hardware/software solution for stream Prefetching in multimedia applications
Multimedia Hardware Architectures 1998, 1998Co-Authors: P Struik, P. Van Der Wolf, Andy D PimentelAbstract:Prefetch techniques may, in general, be applied to reduce the miss rate of a processor's data cache and thereby improve the overall performance of the processor. More in particular, stream Prefetch techniques can be applied to Prefetch data streams that are often encountered in multimedia applications. Stream Prefetch techniques exploit the fact that data from such streams are often accessed in a regular fashion. Implementing a stream Prefetch technique involves two issues, viz. stream combined hardware/software stream Prefetch technique. A special stream-Prefetch Instruction is introduced to alert the hardware that load Instructions access a data stream. Subsequently, Prefetching is handled by the hardware automatically in such a way that the rate at which the data is Prefetched is synchronized with the rate at which the Prefetched data is processed by the application. These kinds of stream Prefetch techniques have been proposed earlier but use Instruction addresses for synchronization. The technique that is introduced in this paper uses a different synchronization mechanism that does not suffer from drawbacks of Instruction address synchronization.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Jean Christophe Beyler - One of the best experts on this subject based on the ideXlab platform.
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Performance driven data cache Prefetching in a dynamic software optimization system
2007Co-Authors: Jean Christophe Beyler, Philippe ClaussAbstract:Software or hardware data cache Prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued Prefetches have to be monitored in order to maximize their positive impact while minimizing their negative impact on performance. In previous proposed dynamic frameworks, the monitoring scheme is either achieved using processor performance counters or using specific hardware. In this work, we propose a Prefetching strategy which does not use any specific hardware component or processor performance counter. Our dynamic framework wants to be portable on any modern processor architecture providing at least a Prefetch Instruction. Opportunity and effectiveness of Prefetching loads is simply guided by the time spent to effectively obtain the data. Every load of a program is monitored periodically and can be either associated to a dynamically inserted Prefetch Instruction or not. It can be associated to a Prefetch Instruction at some disjoint periods of the whole program run as soon as it is efficient. Our framework has been implemented for Itanium-2 machines. It involves several dynamic instrumentations of the binary code whose overhead is limited to only 4% on average. On a large set of benchmarks, our system is able to speed up some programs by 2%--143%.
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ICS - Performance driven data cache Prefetching in a dynamic software optimization system
Proceedings of the 21st annual international conference on Supercomputing - ICS '07, 2007Co-Authors: Jean Christophe Beyler, Philippe ClaussAbstract:Software or hardware data cache Prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued Prefetches have to be monitored in order to maximize their positive impact while minimizing their negative impact on performance. In previous proposed dynamic frameworks, the monitoring scheme is either achieved using processor performance counters or using specific hardware. In this work, we propose a Prefetching strategy which does not use any specific hardware component or processor performance counter. Our dynamic framework wants to be portable on any modern processor architecture providing at least a Prefetch Instruction. Opportunity and effectiveness of Prefetching loads is simply guided by the time spent to effectively obtain the data. Every load of a program is monitored periodically and can be either associated to a dynamically inserted Prefetch Instruction or not. It can be associated to a Prefetch Instruction at some disjoint periods of the whole program run as soon as it is efficient. Our framework has been implemented for Itanium-2 machines. It involves several dynamic instrumentations of the binary code whose overhead is limited to only 4% on average. On a large set of benchmarks, our system is able to speed up some programs by 2%--143%.
Gruss Daniel - One of the best experts on this subject based on the ideXlab platform.
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Speculative Dereferencing of Registers:Reviving Foreshadow
2020Co-Authors: Schwarzl Martin, Schuster Thomas, Schwarz Michael, Gruss DanielAbstract:Since 2016, multiple microarchitectural attacks have exploited an effect that is attributed to Prefetching. These works observe that certain user-space operations can fetch kernel addresses into the cache. Fetching user-inaccessible data into the cache enables KASLR breaks and assists various Meltdown-type attacks, especially Foreshadow. In this paper, we provide a systematic analysis of the root cause of this Prefetching effect. While we confirm the empirical results of previous papers, we show that the attribution to a Prefetching mechanism is fundamentally incorrect in all previous papers describing or exploiting this effect. In particular, neither the Prefetch Instruction nor other user-space Instructions actually Prefetch kernel addresses into the cache, leading to incorrect conclusions and ineffectiveness of proposed defenses. The effect exploited in all of these papers is, in fact, caused by speculative dereferencing of user-space registers in the kernel. Hence, mitigation techniques such as KAISER do not eliminate this leakage as previously believed. Beyond our thorough analysis of these previous works, we also demonstrate new attacks enabled by understanding the root cause, namely an address-translation attack in more restricted contexts, direct leakage of register values in certain scenarios, and the first end-to-end Foreshadow (L1TF) exploit targeting non-L1 data. The latter is effective even with the recommended Foreshadow mitigations enabled and thus revives the Foreshadow attack. We demonstrate that these dereferencing effects exist even on the most recent Intel CPUs with the latest hardware mitigations, and on CPUs previously believed to be unaffected, i.e., ARM, IBM, and AMD CPUs.Comment: 16 pages, 6 figure