The Experts below are selected from a list of 117144 Experts worldwide ranked by ideXlab platform

Alexander V Veidenbaum - One of the best experts on this subject based on the ideXlab platform.

  • dynamic register file resizing and frequency scaling to improve embedded Processor Performance and energy delay efficiency
    Design Automation Conference, 2008
    Co-Authors: Houman Homayoun, Sudeep Pasricha, Mohammad Makhzan, Alexander V Veidenbaum
    Abstract:

    With CMOS scaling leading to ever increasing levels of transistor integration on a chip, designers of high-Performance embedded Processors have ample area available to increase Processor resources in order to improve Performance. However, increasing resource sizes can increase power dissipation and also reduce access time, which can limit maximum achievable operating frequency. In this paper, we explore optimizations for the Processor register file (RF), to improve Performance and reduce the energy-delay product. We show that while increasing the size of the RF can potentially increase the IPC, overall it results in an increase in program execution time. In response we propose L2MRFS -- a dynamic register file resizing scheme in tandem with frequency scaling, which exploits L2 cache misses to noticeably improve Processor Performance (11% on average) and also significantly reduce the energy-delay product (7%).

  • SIGMETRICS - Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium® architecture
    Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '07, 2007
    Co-Authors: Arun Kejariwal, Gerolf F. Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V Veidenbaum
    Abstract:

    Recently SPEC1 released the next generation of its CPU benchmark, widely used by compiler writers and architects for measuring Processor Performance. This calls for characterization of the applications in SPEC CPU2006 to guide the design of future microProcessors. In addition, it necessitates assessing the change in the characteristics of the applications from one suite to another. Although similar studies using the retired SPEC CPU benchmark suites have been done in the past, to the best of our knowledge, a thorough characterization of CPU2006 and its comparison with CPU2000 has not been done so far. In this paper, we present the above; specifically, we analyze IPC (instructions per cycle), L1, L2 data cache misses and branch prediction, especially in CPU2006.

  • comparative characterization of spec cpu2000 and cpu2006 on itanium architecture
    Measurement and Modeling of Computer Systems, 2007
    Co-Authors: Arun Kejariwal, Gerolf F. Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V Veidenbaum
    Abstract:

    Recently SPEC1 released the next generation of its CPU benchmark, widely used by compiler writers and architects for measuring Processor Performance. This calls for characterization of the applications in SPEC CPU2006 to guide the design of future microProcessors. In addition, it necessitates assessing the change in the characteristics of the applications from one suite to another. Although similar studies using the retired SPEC CPU benchmark suites have been done in the past, to the best of our knowledge, a thorough characterization of CPU2006 and its comparison with CPU2000 has not been done so far. In this paper, we present the above; specifically, we analyze IPC (instructions per cycle), L1, L2 data cache misses and branch prediction, especially in CPU2006.

  • ISHPC - A Simple Low-Energy Instruction Wakeup Mechanism
    Lecture Notes in Computer Science, 2003
    Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Mateo Valero
    Abstract:

    Instruction issue consumes a large amount of energy in out of order Processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on Processor Performance. This paper proposes a mechanism for instruction wakeup, which uses a multi-block instruction queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks.

Jacques Demerjian - One of the best experts on this subject based on the ideXlab platform.

  • Robust IoT time series classification with data compression and deep learning
    Neurocomputing EEG Neurocomputing, 2020
    Co-Authors: Joseph Azar, Abdallah Makhoul, Raphael Couturier, Jacques Demerjian
    Abstract:

    Internet of Things (IoT) and wearable systems are very resource limited in terms of power, memory, bandwidth and Processor Performance. Sensor time series compression can be regarded as a direct way to use memory and bandwidth resources efficiently. On the other hand, the time series classification has recently attracted great attention and has found numerous potential uses in areas such as finance, industry and healthcare. This paper investigates the effect of lossy compression techniques on the time series classification task using deep neural networks. Furthermore, this paper proposes an efficient compression approach for univariate and multivariate time series that combines the lifting implementation of the discrete wavelet transform with an error-bound compressor, namely Squeeze (SZ), to attain an optimal trade-off between data compression and data quality.

Demerjian Jacques - One of the best experts on this subject based on the ideXlab platform.

  • Robust IoT time series classification with data compression and deep learning
    HAL CCSD, 2020
    Co-Authors: Azar Joseph, Makhoul Abdallah, Couturier Raphael, Demerjian Jacques
    Abstract:

    International audienceInternet of Things (IoT) and wearable systems are very resource limited in terms of power, memory, bandwidth and Processor Performance. Sensor time series compression can be regarded as a direct way to use memory and bandwidth resources efficiently. On the other hand, the time series classification has recently attracted great attention and has found numerous potential uses in areas such as finance, industry and healthcare. This paper investigates the effect of lossy compression techniques on the time series classification task using deep neural networks. Furthermore, this paper proposes an efficient compression approach for univariate and multivariate time series that combines the lifting implementation of the discrete wavelet transform with an error-bound compressor, namely Squeeze (SZ), to attain an optimal trade-off between data compression and data quality

John Shen - One of the best experts on this subject based on the ideXlab platform.

  • modern Processor design fundamentals of superscalar Processors
    2002
    Co-Authors: John Shen, Mikko H Lipasti
    Abstract:

    Modern Processor Design: Fundamentals of Superscalar Processors is an exciting new first edition from John Shen of Carnegie Mellon University & Intel and Mikko Lipasti of the University of Wisconsin-Madison. This book brings together the numerous microarchitectural techniques for harvesting more instruction-level parallelism (ILP) to achieve better Processor Performance that have been proposed and implemented in real machines. These techniques, as well as the foundational principles behind them, are organized and presented within a clear framework that allows for ease of comprehension. This text is intended for an advanced computer architecture course or a course in superscalar Processor design. It is written at a level appropriate for senior or first year graduate level students.

  • MICRO - Theoretical modeling of superscalar Processor Performance
    Proceedings of the 27th annual international symposium on Microarchitecture - MICRO 27, 1994
    Co-Authors: D.b. Noonburg, John Shen
    Abstract:

    The current trace-driven simulation approach to determine superscalar Processor Performance is widely used but has some shortcomings. Modern benchmarks generate extremely long traces, resulting in problems with data storage, as well as very long simulation run times. More fundamentally, simulation generally does not provide significant insight into the factors that determine Performance or a characterization of their interactions. This paper proposes a theoretical model of superscalar Processor Performance that addresses these shortcomings. Performance is viewed as an interaction of program parallelism and machine parallelism. Both program and machine parallelisms are decomposed into multiple component functions. Methods for measuring or computing these functions are described. The functions are combined to provide a model of the interaction between program and machine parallelisms and an accurate estimate of the Performance. The computed Performance, based on this model, is compared to simulated Performance for six benchmarks from the SPEC 92 suite on several configurations of the IBM RS/6000 instruction set architecture.

  • MICRO - Theoretical modeling of superscalar Processor Performance
    Proceedings of the 27th annual international symposium on Microarchitecture - MICRO 27, 1994
    Co-Authors: D.b. Noonburg, John Shen
    Abstract:

    The current trace-driven simulation approach to determine superscalar Processor Performance is widely used but has some shortcomings. Modern benchmarks generate extremely long traces, resulting in problems with data storage, as well as very long simulation run times. More fundamentally, simulation generally does not provide significant insight into the factors that determine Performance or a characterization of their interactions. This paper proposes a theoretical model of superscalar Processor Performance that addresses these shortcomings. Performance is viewed as an interaction of program parallelism and machine parallelism. Both program and machine parallelisms are decomposed into multiple component functions. Methods for measuring or computing these functions are described. The functions are combined to provide a model of the interaction between program and machine parallelisms and an accurate estimate of the Performance. The computed Performance, based on this model, is compared to simulated Performance for six benchmarks from the SPEC 92 suite on several configurations of the IBM RS/6000 instruction set architecture.

Todd Austin - One of the best experts on this subject based on the ideXlab platform.

  • diva a reliable substrate for deep submicron microarchitecture design
    International Symposium on Microarchitecture, 1999
    Co-Authors: Todd Austin
    Abstract:

    Building a high-Performance microProcessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper, we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microProcessor designs. The approach works by augmenting the commit phase of the Processor pipeline with a functional checker unit. The functional checker verifies the correctness of the core Processor's computation, only permitting correct results to commit. Overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit. We detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core Processor Performance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and electrical verification better than a complex core Processor. Finally, future applications that leverage dynamic verification to increase Processor Performance and availability are suggested.

  • fetch directed instruction prefetching
    International Symposium on Microarchitecture, 1999
    Co-Authors: Glenn Reinman, Brad Calder, Todd Austin
    Abstract:

    Instruction supply is a crucial component of Processor Performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn can help increase instruction supply to the Processor. In this paper we examine a new instruction prefetch architecture called Fetch Directed Prefetching, and compare it to the Performance of next-line prefetching and streaming buffers. This architecture uses a decoupled branch predictor and instruction cache, so the branch predictor can run ahead of the instruction cache fetch. In addition, we examine marking fetch blocks in the branch predictor that are kicked out of the instruction cache, so branch predicted fetch blocks can be accurately prefetched. Finally, we model the use of idle instruction cache ports to filter prefetch requests, thereby saving bus bandwidth to the L2 cache.